4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / sim / vga.fit.summary

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+Fitter Status : Successful - Thu Oct 29 17:00:26 2009
+Quartus II Version : 9.0 Build 132 02/25/2009 SJ Full Version
+Revision Name : vga
+Top-level Entity Name : vga
+Family : Stratix
+Device : EP1S25F672C6
+Timing Models : Final
+Total logic elements : 141 / 25,660 ( < 1 % )
+Total pins : 91 / 474 ( 19 % )
+Total virtual pins : 0
+Total memory bits : 0 / 1,944,576 ( 0 % )
+DSP block 9-bit elements : 0 / 80 ( 0 % )
+Total PLLs : 0 / 6 ( 0 % )
+Total DLLs : 0 / 2 ( 0 % )