--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This SDF file should be used for ModelSim-Altera (VHDL) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "vga")
+ (DATE "10/29/2009 17:00:56")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE clk_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (868:868:868) (868:868:868))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE reset_pin_in.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (1295:1295:1295) (1295:1295:1295))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4768:4768:4768) (4768:4768:4768))
+ (PORT datab (469:469:469) (469:469:469))
+ (PORT datac (486:486:486) (486:486:486))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\dly_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4768:4768:4768) (4768:4768:4768))
+ (PORT datab (465:465:465) (465:465:465))
+ (PORT datac (485:485:485) (485:485:485))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\dly_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4777:4777:4777) (4777:4777:4777))
+ (PORT datab (476:476:476) (476:476:476))
+ (PORT datac (490:490:490) (490:490:490))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2355:2355:2355) (2355:2355:2355))
+ (PORT datad (1131:1131:1131) (1131:1131:1131))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2445:2445:2445) (2445:2445:2445))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1704:1704:1704) (1704:1704:1704))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1794:1794:1794) (1794:1794:1794))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1707:1707:1707) (1707:1707:1707))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1797:1797:1797) (1797:1797:1797))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1709:1709:1709) (1709:1709:1709))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1799:1799:1799) (1799:1799:1799))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1712:1712:1712) (1712:1712:1712))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1802:1802:1802) (1802:1802:1802))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1715:1715:1715) (1715:1715:1715))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1805:1805:1805) (1805:1805:1805))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1722:1722:1722) (1722:1722:1722))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1812:1812:1812) (1812:1812:1812))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (665:665:665) (665:665:665))
+ (PORT datab (628:628:628) (628:628:628))
+ (PORT datac (650:650:650) (650:650:650))
+ (PORT datad (644:644:644) (644:644:644))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1721:1721:1721) (1721:1721:1721))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1811:1811:1811) (1811:1811:1811))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1719:1719:1719) (1719:1719:1719))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1809:1809:1809) (1809:1809:1809))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1718:1718:1718) (1718:1718:1718))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1808:1808:1808) (1808:1808:1808))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1717:1717:1717) (1717:1717:1717))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1759:1759:1759) (1759:1759:1759))
+ (PORT datac (1807:1807:1807) (1807:1807:1807))
+ (PORT sclr (1308:1308:1308) (1308:1308:1308))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (663:663:663) (663:663:663))
+ (PORT datab (609:609:609) (609:609:609))
+ (PORT datac (1034:1034:1034) (1034:1034:1034))
+ (PORT datad (636:636:636) (636:636:636))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (963:963:963) (963:963:963))
+ (PORT datab (934:934:934) (934:934:934))
+ (PORT datac (374:374:374) (374:374:374))
+ (PORT datad (351:351:351) (351:351:351))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1446:1446:1446) (1446:1446:1446))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (626:626:626) (626:626:626))
+ (PORT datad (1675:1675:1675) (1675:1675:1675))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (640:640:640) (640:640:640))
+ (PORT datab (610:610:610) (610:610:610))
+ (PORT datac (1035:1035:1035) (1035:1035:1035))
+ (PORT datad (652:652:652) (652:652:652))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (924:924:924) (924:924:924))
+ (PORT datab (627:627:627) (627:627:627))
+ (PORT datac (371:371:371) (371:371:371))
+ (PORT datad (350:350:350) (350:350:350))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (665:665:665) (665:665:665))
+ (PORT datab (649:649:649) (649:649:649))
+ (PORT datac (1030:1030:1030) (1030:1030:1030))
+ (PORT datad (636:636:636) (636:636:636))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (637:637:637) (637:637:637))
+ (PORT datab (604:604:604) (604:604:604))
+ (PORT datac (650:650:650) (650:650:650))
+ (PORT datad (637:637:637) (637:637:637))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (656:656:656) (656:656:656))
+ (PORT datab (929:929:929) (929:929:929))
+ (PORT datac (364:364:364) (364:364:364))
+ (PORT datad (353:353:353) (353:353:353))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (706:706:706) (706:706:706))
+ (PORT datab (346:346:346) (346:346:346))
+ (PORT datac (926:926:926) (926:926:926))
+ (PORT datad (351:351:351) (351:351:351))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1016:1016:1016) (1016:1016:1016))
+ (PORT sclr (2456:2456:2456) (2456:2456:2456))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1257:1257:1257) (1257:1257:1257))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (960:960:960) (960:960:960))
+ (PORT datab (903:903:903) (903:903:903))
+ (PORT datac (959:959:959) (959:959:959))
+ (PORT datad (943:943:943) (943:943:943))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (439:439:439) (439:439:439))
+ (PORT datac (1416:1416:1416) (1416:1416:1416))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2436:2436:2436) (2436:2436:2436))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (927:927:927) (927:927:927))
+ (PORT datab (928:928:928) (928:928:928))
+ (PORT datad (996:996:996) (996:996:996))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (592:592:592) (592:592:592))
+ (PORT datab (368:368:368) (368:368:368))
+ (PORT datac (462:462:462) (462:462:462))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (956:956:956) (956:956:956))
+ (PORT datab (909:909:909) (909:909:909))
+ (PORT datac (910:910:910) (910:910:910))
+ (PORT datad (921:921:921) (921:921:921))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (903:903:903) (903:903:903))
+ (PORT datac (951:951:951) (951:951:951))
+ (PORT datad (962:962:962) (962:962:962))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (448:448:448) (448:448:448))
+ (PORT datab (377:377:377) (377:377:377))
+ (PORT datac (556:556:556) (556:556:556))
+ (PORT datad (568:568:568) (568:568:568))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1669:1669:1669) (1669:1669:1669))
+ (PORT datab (554:554:554) (554:554:554))
+ (PORT datac (374:374:374) (374:374:374))
+ (PORT datad (346:346:346) (346:346:346))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (987:987:987) (987:987:987))
+ (PORT datad (558:558:558) (558:558:558))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2436:2436:2436) (2436:2436:2436))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (553:553:553) (553:553:553))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2436:2436:2436) (2436:2436:2436))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4777:4777:4777) (4777:4777:4777))
+ (PORT datab (477:477:477) (477:477:477))
+ (PORT datac (969:969:969) (969:969:969))
+ (PORT datad (896:896:896) (896:896:896))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (946:946:946) (946:946:946))
+ (PORT datac (955:955:955) (955:955:955))
+ (PORT datad (921:921:921) (921:921:921))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (878:878:878) (878:878:878))
+ (PORT datab (367:367:367) (367:367:367))
+ (PORT datac (456:456:456) (456:456:456))
+ (PORT datad (385:385:385) (385:385:385))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2436:2436:2436) (2436:2436:2436))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (449:449:449) (449:449:449))
+ (PORT datab (371:371:371) (371:371:371))
+ (PORT datac (862:862:862) (862:862:862))
+ (PORT datad (571:571:571) (571:571:571))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2436:2436:2436) (2436:2436:2436))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2348:2348:2348) (2348:2348:2348))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4774:4774:4774) (4774:4774:4774))
+ (PORT datab (475:475:475) (475:475:475))
+ (PORT datac (489:489:489) (489:489:489))
+ (PORT datad (1416:1416:1416) (1416:1416:1416))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (940:940:940) (940:940:940))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2229:2229:2229) (2229:2229:2229))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (988:988:988) (988:988:988))
+ (PORT datab (929:929:929) (929:929:929))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (937:937:937) (937:937:937))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2229:2229:2229) (2229:2229:2229))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (936:936:936) (936:936:936))
+ (PORT datab (700:700:700) (700:700:700))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (910:910:910) (910:910:910))
+ (PORT datad (535:535:535) (535:535:535))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2199:2199:2199) (2199:2199:2199))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (993:993:993) (993:993:993))
+ (PORT datab (963:963:963) (963:963:963))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (451:451:451) (451:451:451))
+ (PORT datab (1009:1009:1009) (1009:1009:1009))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (576:576:576) (576:576:576))
+ (PORT datac (365:365:365) (365:365:365))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2244:2244:2244) (2244:2244:2244))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1010:1010:1010) (1010:1010:1010))
+ (PORT datab (980:980:980) (980:980:980))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (890:890:890) (890:890:890))
+ (PORT datac (858:858:858) (858:858:858))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2199:2199:2199) (2199:2199:2199))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (438:438:438) (438:438:438))
+ (PORT datab (960:960:960) (960:960:960))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (360:360:360) (360:360:360))
+ (PORT datac (938:938:938) (938:938:938))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2229:2229:2229) (2229:2229:2229))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datab (647:647:647) (647:647:647))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1462:1462:1462) (1462:1462:1462))
+ (PORT datac (939:939:939) (939:939:939))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1054:1054:1054) (1054:1054:1054))
+ (PORT datab (917:917:917) (917:917:917))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (439:439:439) (439:439:439))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (366:366:366) (366:366:366))
+ (PORT datac (572:572:572) (572:572:572))
+ (PORT datad (1463:1463:1463) (1463:1463:1463))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un2_column_counter_next_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (924:924:924) (924:924:924))
+ (PORT datad (426:426:426) (426:426:426))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (941:941:941) (941:941:941))
+ (PORT datad (347:347:347) (347:347:347))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2229:2229:2229) (2229:2229:2229))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (966:966:966) (966:966:966))
+ (PORT datac (620:620:620) (620:620:620))
+ (PORT datad (619:619:619) (619:619:619))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1013:1013:1013) (1013:1013:1013))
+ (PORT datab (350:350:350) (350:350:350))
+ (PORT datac (373:373:373) (373:373:373))
+ (PORT datad (1014:1014:1014) (1014:1014:1014))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (954:954:954) (954:954:954))
+ (PORT datab (651:651:651) (651:651:651))
+ (PORT datac (933:933:933) (933:933:933))
+ (PORT datad (347:347:347) (347:347:347))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (890:890:890) (890:890:890))
+ (PORT datac (881:881:881) (881:881:881))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2199:2199:2199) (2199:2199:2199))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (933:933:933) (933:933:933))
+ (PORT datad (685:685:685) (685:685:685))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_i_o3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1016:1016:1016) (1016:1016:1016))
+ (PORT datab (917:917:917) (917:917:917))
+ (PORT datac (1056:1056:1056) (1056:1056:1056))
+ (PORT datad (992:992:992) (992:992:992))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|g_next_i_o3_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datad (429:429:429) (429:429:429))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1046:1046:1046) (1046:1046:1046))
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (1004:1004:1004) (1004:1004:1004))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1094:1094:1094) (1094:1094:1094))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1004:1004:1004) (1004:1004:1004))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1094:1094:1094) (1094:1094:1094))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1003:1003:1003) (1003:1003:1003))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1093:1093:1093) (1093:1093:1093))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1002:1002:1002) (1002:1002:1002))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1092:1092:1092) (1092:1092:1092))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1001:1001:1001) (1001:1001:1001))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1091:1091:1091) (1091:1091:1091))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1002:1002:1002) (1002:1002:1002))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1092:1092:1092) (1092:1092:1092))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (634:634:634) (634:634:634))
+ (PORT datab (647:647:647) (647:647:647))
+ (PORT datac (940:940:940) (940:940:940))
+ (PORT datad (976:976:976) (976:976:976))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (1002:1002:1002) (1002:1002:1002))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1092:1092:1092) (1092:1092:1092))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1001:1001:1001) (1001:1001:1001))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1091:1091:1091) (1091:1091:1091))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1001:1001:1001) (1001:1001:1001))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1091:1091:1091) (1091:1091:1091))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (999:999:999) (999:999:999))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1429:1429:1429) (1429:1429:1429))
+ (PORT datac (1089:1089:1089) (1089:1089:1089))
+ (PORT sclr (1316:1316:1316) (1316:1316:1316))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (996:996:996) (996:996:996))
+ (PORT datab (971:971:971) (971:971:971))
+ (PORT datac (652:652:652) (652:652:652))
+ (PORT datad (996:996:996) (996:996:996))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1000:1000:1000) (1000:1000:1000))
+ (PORT datab (345:345:345) (345:345:345))
+ (PORT datac (1071:1071:1071) (1071:1071:1071))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|G_16\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1066:1066:1066) (1066:1066:1066))
+ (PORT datab (1052:1052:1052) (1052:1052:1052))
+ (PORT datac (456:456:456) (456:456:456))
+ (PORT datad (354:354:354) (354:354:354))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (624:624:624) (624:624:624))
+ (PORT datab (584:584:584) (584:584:584))
+ (PORT datac (960:960:960) (960:960:960))
+ (PORT datad (622:622:622) (622:622:622))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (629:629:629) (629:629:629))
+ (PORT datab (639:639:639) (639:639:639))
+ (PORT datac (656:656:656) (656:656:656))
+ (PORT datad (619:619:619) (619:619:619))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1053:1053:1053) (1053:1053:1053))
+ (PORT datac (979:979:979) (979:979:979))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (886:886:886) (886:886:886))
+ (PORT datad (854:854:854) (854:854:854))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (947:947:947) (947:947:947))
+ (PORT datad (699:699:699) (699:699:699))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1803:1803:1803) (1803:1803:1803))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1081:1081:1081) (1081:1081:1081))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (969:969:969) (969:969:969))
+ (PORT datab (673:673:673) (673:673:673))
+ (PORT datac (364:364:364) (364:364:364))
+ (PORT datad (444:444:444) (444:444:444))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1803:1803:1803) (1803:1803:1803))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1081:1081:1081) (1081:1081:1081))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (674:674:674) (674:674:674))
+ (PORT datab (610:610:610) (610:610:610))
+ (PORT datac (657:657:657) (657:657:657))
+ (PORT datad (683:683:683) (683:683:683))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (924:924:924) (924:924:924))
+ (PORT datac (701:701:701) (701:701:701))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (431:431:431) (431:431:431))
+ (PORT datac (877:877:877) (877:877:877))
+ (PORT datad (253:253:253) (253:253:253))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (433:433:433) (433:433:433))
+ (PORT datab (871:871:871) (871:871:871))
+ (PORT datac (863:863:863) (863:863:863))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (968:968:968) (968:968:968))
+ (PORT datab (435:435:435) (435:435:435))
+ (PORT datac (700:700:700) (700:700:700))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (972:972:972) (972:972:972))
+ (PORT datab (894:894:894) (894:894:894))
+ (PORT datac (1516:1516:1516) (1516:1516:1516))
+ (PORT datad (565:565:565) (565:565:565))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1606:1606:1606) (1606:1606:1606))
+ (PORT sclr (1138:1138:1138) (1138:1138:1138))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1299:1299:1299) (1299:1299:1299))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1038:1038:1038) (1038:1038:1038))
+ (PORT datab (351:351:351) (351:351:351))
+ (PORT datac (582:582:582) (582:582:582))
+ (PORT datad (564:564:564) (564:564:564))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (888:888:888) (888:888:888))
+ (PORT datab (671:671:671) (671:671:671))
+ (PORT datac (703:703:703) (703:703:703))
+ (PORT datad (960:960:960) (960:960:960))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1803:1803:1803) (1803:1803:1803))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1081:1081:1081) (1081:1081:1081))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (346:346:346) (346:346:346))
+ (PORT datac (359:359:359) (359:359:359))
+ (PORT datad (992:992:992) (992:992:992))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (354:354:354) (354:354:354))
+ (PORT datab (1046:1046:1046) (1046:1046:1046))
+ (PORT datac (451:451:451) (451:451:451))
+ (PORT datad (944:944:944) (944:944:944))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|d_set_vsync_counter_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (991:991:991) (991:991:991))
+ (PORT datad (946:946:946) (946:946:946))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (636:636:636) (636:636:636))
+ (PORT datab (4638:4638:4638) (4638:4638:4638))
+ (PORT datac (363:363:363) (363:363:363))
+ (PORT datad (613:613:613) (613:613:613))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1033:1033:1033) (1033:1033:1033))
+ (PORT datab (610:610:610) (610:610:610))
+ (PORT datac (662:662:662) (662:662:662))
+ (PORT datad (613:613:613) (613:613:613))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1612:1612:1612) (1612:1612:1612))
+ (PORT datab (1692:1692:1692) (1692:1692:1692))
+ (PORT datac (1412:1412:1412) (1412:1412:1412))
+ (PORT datad (1529:1529:1529) (1529:1529:1529))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1537:1537:1537) (1537:1537:1537))
+ (PORT datab (1691:1691:1691) (1691:1691:1691))
+ (PORT datad (1518:1518:1518) (1518:1518:1518))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (428:428:428) (428:428:428))
+ (PORT datad (1520:1520:1520) (1520:1520:1520))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2477:2477:2477) (2477:2477:2477))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (968:968:968) (968:968:968))
+ (PORT datac (1401:1401:1401) (1401:1401:1401))
+ (PORT datad (1404:1404:1404) (1404:1404:1404))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1628:1628:1628) (1628:1628:1628))
+ (PORT datac (1512:1512:1512) (1512:1512:1512))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1737:1737:1737) (1737:1737:1737))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (PORT ena (1092:1092:1092) (1092:1092:1092))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|r_next_i_o7_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (427:427:427) (427:427:427))
+ (PORT datac (930:930:930) (930:930:930))
+ (PORT datad (1453:1453:1453) (1453:1453:1453))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|N_4_i_0_g0_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (895:895:895) (895:895:895))
+ (PORT datab (648:648:648) (648:648:648))
+ (PORT datac (650:650:650) (650:650:650))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|r_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (891:891:891) (891:891:891))
+ (PORT datab (618:618:618) (618:618:618))
+ (PORT datac (551:551:551) (551:551:551))
+ (PORT datad (852:852:852) (852:852:852))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|r_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5163:5163:5163) (5163:5163:5163))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|N_23_i_0_g0_a_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (698:698:698) (698:698:698))
+ (PORT datab (349:349:349) (349:349:349))
+ (PORT datac (934:934:934) (934:934:934))
+ (PORT datad (879:879:879) (879:879:879))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|g_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (990:990:990) (990:990:990))
+ (PORT datab (621:621:621) (621:621:621))
+ (PORT datac (860:860:860) (860:860:860))
+ (PORT datad (899:899:899) (899:899:899))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|g_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5163:5163:5163) (5163:5163:5163))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_next_i_a7_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (449:449:449) (449:449:449))
+ (PORT datab (436:436:436) (436:436:436))
+ (PORT datac (1056:1056:1056) (1056:1056:1056))
+ (PORT datad (868:868:868) (868:868:868))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|N_6_i_0_g0_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1060:1060:1060) (1060:1060:1060))
+ (PORT datab (435:435:435) (435:435:435))
+ (PORT datac (557:557:557) (557:557:557))
+ (PORT datad (587:587:587) (587:587:587))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (546:546:546) (546:546:546))
+ (PORT datab (535:535:535) (535:535:535))
+ (PORT datac (559:559:559) (559:559:559))
+ (PORT datad (631:631:631) (631:631:631))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_control_unit\|b_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5163:5163:5163) (5163:5163:5163))
+ (PORT clk (2359:2359:2359) (2359:2359:2359))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_hsync_state_3_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1628:1628:1628) (1628:1628:1628))
+ (PORT datac (1512:1512:1512) (1512:1512:1512))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1415:1415:1415) (1415:1415:1415))
+ (PORT datab (335:335:335) (335:335:335))
+ (PORT datac (1460:1460:1460) (1460:1460:1460))
+ (PORT datad (431:431:431) (431:431:431))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (364:364:364) (364:364:364))
+ (PORT datab (4641:4641:4641) (4641:4641:4641))
+ (PORT datac (635:635:635) (635:635:635))
+ (PORT datad (616:616:616) (616:616:616))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_vsync_state_2_0_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1513:1513:1513) (1513:1513:1513))
+ (PORT datad (421:421:421) (421:421:421))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_1_0_0_0_g1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (610:610:610) (610:610:610))
+ (PORT datab (634:634:634) (634:634:634))
+ (PORT datac (403:403:403) (403:403:403))
+ (PORT datad (649:649:649) (649:649:649))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4772:4772:4772) (4772:4772:4772))
+ (PORT datab (473:473:473) (473:473:473))
+ (PORT datac (488:488:488) (488:488:488))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (4776:4776:4776) (4776:4776:4776))
+ (PORT datab (1496:1496:1496) (1496:1496:1496))
+ (PORT datac (490:490:490) (490:490:490))
+ (PORT datad (660:660:660) (660:660:660))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_a_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1009:1009:1009) (1009:1009:1009))
+ (PORT datab (556:556:556) (556:556:556))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (434:434:434) (434:434:434))
+ (PORT datab (426:426:426) (426:426:426))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (614:614:614) (614:614:614))
+ (PORT datad (355:355:355) (355:355:355))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1696:1696:1696) (1696:1696:1696))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_1_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (747:747:747) (747:747:747))
+ (PORT datab (342:342:342) (342:342:342))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (664:664:664) (664:664:664))
+ (PORT datab (695:695:695) (695:695:695))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (610:610:610) (610:610:610))
+ (PORT datad (542:542:542) (542:542:542))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1696:1696:1696) (1696:1696:1696))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (646:646:646) (646:646:646))
+ (PORT datab (631:631:631) (631:631:631))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (596:596:596) (596:596:596))
+ (PORT datac (368:368:368) (368:368:368))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1696:1696:1696) (1696:1696:1696))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (678:678:678) (678:678:678))
+ (PORT datab (679:679:679) (679:679:679))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (613:613:613) (613:613:613))
+ (PORT datad (541:541:541) (541:541:541))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1696:1696:1696) (1696:1696:1696))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (646:646:646) (646:646:646))
+ (PORT datab (942:942:942) (942:942:942))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (353:353:353) (353:353:353))
+ (PORT datac (928:928:928) (928:928:928))
+ (PORT datad (837:837:837) (837:837:837))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (671:671:671) (671:671:671))
+ (PORT datab (588:588:588) (588:588:588))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (540:540:540) (540:540:540))
+ (PORT datad (572:572:572) (572:572:572))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1689:1689:1689) (1689:1689:1689))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (682:682:682) (682:682:682))
+ (PORT datab (681:681:681) (681:681:681))
+ (PORT datad (999:999:999) (999:999:999))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (668:668:668) (668:668:668))
+ (PORT datab (702:702:702) (702:702:702))
+ (PORT datac (437:437:437) (437:437:437))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (611:611:611) (611:611:611))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1696:1696:1696) (1696:1696:1696))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_9_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (636:636:636) (636:636:636))
+ (PORT datad (660:660:660) (660:660:660))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (565:565:565) (565:565:565))
+ (PORT datad (538:538:538) (538:538:538))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1689:1689:1689) (1689:1689:1689))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (674:674:674) (674:674:674))
+ (PORT datab (341:341:341) (341:341:341))
+ (PORT datac (653:653:653) (653:653:653))
+ (PORT datad (662:662:662) (662:662:662))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (557:557:557) (557:557:557))
+ (PORT datad (533:533:533) (533:533:533))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (1689:1689:1689) (1689:1689:1689))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2323:2323:2323) (2323:2323:2323))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4282:4282:4282) (4282:4282:4282))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4282:4282:4282) (4282:4282:4282))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE r2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4282:4282:4282) (4282:4282:4282))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2951:2951:2951) (2951:2951:2951))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2951:2951:2951) (2951:2951:2951))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE g2_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2951:2951:2951) (2951:2951:2951))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b0_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2828:2828:2828) (2828:2828:2828))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE b1_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2828:2828:2828) (2828:2828:2828))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE hsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2955:2955:2955) (2955:2955:2955))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE vsync_pin_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2606:2606:2606) (2606:2606:2606))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1363:1363:1363) (1363:1363:1363))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4309:4309:4309) (4309:4309:4309))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3697:3697:3697) (3697:3697:3697))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1273:1273:1273) (1273:1273:1273))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1273:1273:1273) (1273:1273:1273))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1363:1363:1363) (1363:1363:1363))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1363:1363:1363) (1363:1363:1363))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3254:3254:3254) (3254:3254:3254))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3254:3254:3254) (3254:3254:3254))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3697:3697:3697) (3697:3697:3697))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_10_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3842:3842:3842) (3842:3842:3842))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_11_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3830:3830:3830) (3830:3830:3830))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_out_12_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3254:3254:3254) (3254:3254:3254))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\seven_seg_pin_tri_13_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1363:1363:1363) (1363:1363:1363))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_hsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2955:2955:2955) (2955:2955:2955))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_vsync_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2606:2606:2606) (2606:2606:2606))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2176:2176:2176) (2176:2176:2176))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1905:1905:1905) (1905:1905:1905))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2327:2327:2327) (2327:2327:2327))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2207:2207:2207) (2207:2207:2207))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2378:2378:2378) (2378:2378:2378))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3095:3095:3095) (3095:3095:3095))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1888:1888:1888) (1888:1888:1888))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3062:3062:3062) (3062:3062:3062))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1984:1984:1984) (1984:1984:1984))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_column_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2982:2982:2982) (2982:2982:2982))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2120:2120:2120) (2120:2120:2120))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1873:1873:1873) (1873:1873:1873))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2469:2469:2469) (2469:2469:2469))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2149:2149:2149) (2149:2149:2149))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1892:1892:1892) (1892:1892:1892))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2139:2139:2139) (2139:2139:2139))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2130:2130:2130) (2130:2130:2130))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2400:2400:2400) (2400:2400:2400))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_line_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2376:2376:2376) (2376:2376:2376))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_column_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3450:3450:3450) (3450:3450:3450))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_line_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2524:2524:2524) (2524:2524:2524))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2189:2189:2189) (2189:2189:2189))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2078:2078:2078) (2078:2078:2078))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2133:2133:2133) (2133:2133:2133))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2126:2126:2126) (2126:2126:2126))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2313:2313:2313) (2313:2313:2313))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2116:2116:2116) (2116:2116:2116))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2128:2128:2128) (2128:2128:2128))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2167:2167:2167) (2167:2167:2167))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2171:2171:2171) (2171:2171:2171))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2340:2340:2340) (2340:2340:2340))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2402:2402:2402) (2402:2402:2402))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2446:2446:2446) (2446:2446:2446))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2471:2471:2471) (2471:2471:2471))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2446:2446:2446) (2446:2446:2446))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2469:2469:2469) (2469:2469:2469))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1665:1665:1665) (1665:1665:1665))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2212:2212:2212) (2212:2212:2212))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_7_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2397:2397:2397) (2397:2397:2397))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_8_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2401:2401:2401) (2401:2401:2401))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_counter_out_9_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2394:2394:2394) (2394:2394:2394))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_hsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2047:2047:2047) (2047:2047:2047))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_set_vsync_counter_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2911:2911:2911) (2911:2911:2911))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_h_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2355:2355:2355) (2355:2355:2355))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_v_enable_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2730:2730:2730) (2730:2730:2730))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_r_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4250:4250:4250) (4250:4250:4250))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_g_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2951:2951:2951) (2951:2951:2951))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_b_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2828:2828:2828) (2828:2828:2828))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3434:3434:3434) (3434:3434:3434))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2465:2465:2465) (2465:2465:2465))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2351:2351:2351) (2351:2351:2351))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2196:2196:2196) (2196:2196:2196))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2188:2188:2188) (2188:2188:2188))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3450:3450:3450) (3450:3450:3450))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_hsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2303:2303:2303) (2303:2303:2303))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_6_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2148:2148:2148) (2148:2148:2148))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_5_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2482:2482:2482) (2482:2482:2482))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_4_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2399:2399:2399) (2399:2399:2399))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_3_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3927:3927:3927) (3927:3927:3927))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_2_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2404:2404:2404) (2404:2404:2404))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_1_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2524:2524:2524) (2524:2524:2524))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE \\d_vsync_state_out_0_\\.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3107:3107:3107) (3107:3107:3107))
+ (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE d_state_clk_out.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2588:2588:2588) (2588:2588:2588))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+)
projects / dide_16.git / blobdiff