--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:00:51 2009 " "Info: Processing started: Thu Oct 29 17:00:51 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_pin " "Info: Assuming node \"clk_pin\" is an undefined clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "clk_pin" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_pin register vga_driver:vga_driver_unit\|vsync_counter_4 register vga_driver:vga_driver_unit\|vsync_state_3 191.53 MHz 5.221 ns Internal " "Info: Clock \"clk_pin\" has Internal fmax of 191.53 MHz between source register \"vga_driver:vga_driver_unit\|vsync_counter_4\" and destination register \"vga_driver:vga_driver_unit\|vsync_state_3\" (period= 5.221 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.035 ns + Longest register register " "Info: + Longest register to register delay is 5.035 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|vsync_counter_4 1 REG LC_X37_Y35_N4 6 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit\|vsync_counter_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.033 ns) + CELL(0.459 ns) 1.492 ns vga_driver:vga_driver_unit\|un12_vsync_counter_7 2 COMB LC_X38_Y35_N7 3 " "Info: 2: + IC(1.033 ns) + CELL(0.459 ns) = 1.492 ns; Loc. = LC_X38_Y35_N7; Fanout = 3; COMB Node = 'vga_driver:vga_driver_unit\|un12_vsync_counter_7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.492 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 243 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.854 ns) + CELL(0.087 ns) 2.433 ns vga_driver:vga_driver_unit\|un14_vsync_counter_8 3 COMB LC_X36_Y35_N1 4 " "Info: 3: + IC(0.854 ns) + CELL(0.087 ns) = 2.433 ns; Loc. = LC_X36_Y35_N1; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit\|un14_vsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.941 ns" { vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 251 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.565 ns) + CELL(0.087 ns) 3.085 ns vga_driver:vga_driver_unit\|vsync_state_next_1_sqmuxa_3 4 COMB LC_X35_Y35_N6 1 " "Info: 4: + IC(0.565 ns) + CELL(0.087 ns) = 3.085 ns; Loc. = LC_X35_Y35_N6; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit\|vsync_state_next_1_sqmuxa_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.652 ns" { vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 261 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.564 ns) + CELL(0.087 ns) 3.736 ns vga_driver:vga_driver_unit\|vsync_state_next_2_sqmuxa 5 COMB LC_X36_Y35_N7 5 " "Info: 5: + IC(0.564 ns) + CELL(0.087 ns) = 3.736 ns; Loc. = LC_X36_Y35_N7; Fanout = 5; COMB Node = 'vga_driver:vga_driver_unit\|vsync_state_next_2_sqmuxa'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.651 ns" { vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 242 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.573 ns) + CELL(0.726 ns) 5.035 ns vga_driver:vga_driver_unit\|vsync_state_3 6 REG LC_X35_Y35_N6 5 " "Info: 6: + IC(0.573 ns) + CELL(0.726 ns) = 5.035 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.299 ns" { vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.446 ns ( 28.72 % ) " "Info: Total cell delay = 1.446 ns ( 28.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.589 ns ( 71.28 % ) " "Info: Total interconnect delay = 3.589 ns ( 71.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 {} vga_driver:vga_driver_unit|un12_vsync_counter_7 {} vga_driver:vga_driver_unit|un14_vsync_counter_8 {} vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 {} vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 1.033ns 0.854ns 0.565ns 0.564ns 0.573ns } { 0.000ns 0.459ns 0.087ns 0.087ns 0.087ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.191 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_pin\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|vsync_state_3 2 REG LC_X35_Y35_N6 5 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N6; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.191 ns - Longest register " "Info: - Longest clock path from clock \"clk_pin\" to source register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|vsync_counter_4 2 REG LC_X37_Y35_N4 6 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X37_Y35_N4; Fanout = 6; REG Node = 'vga_driver:vga_driver_unit\|vsync_counter_4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 134 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 vga_driver:vga_driver_unit|un12_vsync_counter_7 vga_driver:vga_driver_unit|un14_vsync_counter_8 vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.035 ns" { vga_driver:vga_driver_unit|vsync_counter_4 {} vga_driver:vga_driver_unit|un12_vsync_counter_7 {} vga_driver:vga_driver_unit|un14_vsync_counter_8 {} vga_driver:vga_driver_unit|vsync_state_next_1_sqmuxa_3 {} vga_driver:vga_driver_unit|vsync_state_next_2_sqmuxa {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 1.033ns 0.854ns 0.565ns 0.564ns 0.573ns } { 0.000ns 0.459ns 0.087ns 0.087ns 0.087ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_3 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|vsync_counter_4 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_counter_4 {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga_driver:vga_driver_unit\|hsync_state_3 reset_pin clk_pin 6.710 ns register " "Info: tsu for register \"vga_driver:vga_driver_unit\|hsync_state_3\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is 6.710 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.916 ns + Longest pin register " "Info: + Longest pin to register delay is 9.916 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.459 ns) 6.531 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.236 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.669 ns) + CELL(0.459 ns) 8.659 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X29_Y33_N4 6 " "Info: 3: + IC(1.669 ns) + CELL(0.459 ns) = 8.659 ns; Loc. = LC_X29_Y33_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.128 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 252 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.531 ns) + CELL(0.726 ns) 9.916 ns vga_driver:vga_driver_unit\|hsync_state_3 4 REG LC_X28_Y33_N3 5 " "Info: 4: + IC(0.531 ns) + CELL(0.726 ns) = 9.916 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.257 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.939 ns ( 29.64 % ) " "Info: Total cell delay = 2.939 ns ( 29.64 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.977 ns ( 70.36 % ) " "Info: Total interconnect delay = 6.977 ns ( 70.36 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.916 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.916 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 4.777ns 1.669ns 0.531ns } { 0.000ns 1.295ns 0.459ns 0.459ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.216 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_pin\" to destination register is 3.216 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.788 ns) + CELL(0.560 ns) 3.216 ns vga_driver:vga_driver_unit\|hsync_state_3 2 REG LC_X28_Y33_N3 5 " "Info: 2: + IC(1.788 ns) + CELL(0.560 ns) = 3.216 ns; Loc. = LC_X28_Y33_N3; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_3'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.348 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 117 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.40 % ) " "Info: Total cell delay = 1.428 ns ( 44.40 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.788 ns ( 55.60 % ) " "Info: Total interconnect delay = 1.788 ns ( 55.60 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.216 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.216 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 1.788ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.916 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.916 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 4.777ns 1.669ns 0.531ns } { 0.000ns 1.295ns 0.459ns 0.459ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.216 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_3 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.216 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_3 {} } { 0.000ns 0.000ns 1.788ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_pin seven_seg_pin\[1\] dly_counter\[0\] 10.979 ns register " "Info: tco from clock \"clk_pin\" to destination pin \"seven_seg_pin\[1\]\" through register \"dly_counter\[0\]\" is 10.979 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to source register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns dly_counter\[0\] 2 REG LC_X35_Y35_N5 10 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} dly_counter[0] {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.612 ns + Longest register pin " "Info: + Longest register to pin delay is 7.612 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns dly_counter\[0\] 1 REG LC_X35_Y35_N5 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y35_N5; Fanout = 10; REG Node = 'dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.476 ns) + CELL(0.332 ns) 0.808 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(0.476 ns) + CELL(0.332 ns) = 0.808 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.808 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(2.495 ns) 7.612 ns seven_seg_pin\[1\] 3 PIN PIN_M9 0 " "Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 7.612 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.804 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3470 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.827 ns ( 37.14 % ) " "Info: Total cell delay = 2.827 ns ( 37.14 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.785 ns ( 62.86 % ) " "Info: Total interconnect delay = 4.785 ns ( 62.86 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.612 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.612 ns" { dly_counter[0] {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.476ns 4.309ns } { 0.000ns 0.332ns 2.495ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} dly_counter[0] {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.612 ns" { dly_counter[0] vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.612 ns" { dly_counter[0] {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.476ns 4.309ns } { 0.000ns 0.332ns 2.495ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset_pin seven_seg_pin\[1\] 13.335 ns Longest " "Info: Longest tpd from source pin \"reset_pin\" to destination pin \"seven_seg_pin\[1\]\" is 13.335 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.777 ns) + CELL(0.459 ns) 6.531 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X35_Y35_N2 32 " "Info: 2: + IC(4.777 ns) + CELL(0.459 ns) = 6.531 ns; Loc. = LC_X35_Y35_N2; Fanout = 32; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.236 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.309 ns) + CELL(2.495 ns) 13.335 ns seven_seg_pin\[1\] 3 PIN PIN_M9 0 " "Info: 3: + IC(4.309 ns) + CELL(2.495 ns) = 13.335 ns; Loc. = PIN_M9; Fanout = 0; PIN Node = 'seven_seg_pin\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.804 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3470 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.249 ns ( 31.86 % ) " "Info: Total cell delay = 4.249 ns ( 31.86 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.086 ns ( 68.14 % ) " "Info: Total interconnect delay = 9.086 ns ( 68.14 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "13.335 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "13.335 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[1] {} } { 0.000ns 0.000ns 4.777ns 4.309ns } { 0.000ns 1.295ns 0.459ns 2.495ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "vga_driver:vga_driver_unit\|h_sync reset_pin clk_pin -3.134 ns register " "Info: th for register \"vga_driver:vga_driver_unit\|h_sync\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is -3.134 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.191 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to destination register is 3.191 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 63 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 63; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3458 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.763 ns) + CELL(0.560 ns) 3.191 ns vga_driver:vga_driver_unit\|h_sync 2 REG LC_X34_Y35_N2 3 " "Info: 2: + IC(1.763 ns) + CELL(0.560 ns) = 3.191 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit\|h_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.323 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 44.75 % ) " "Info: Total cell delay = 1.428 ns ( 44.75 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.763 ns ( 55.25 % ) " "Info: Total interconnect delay = 1.763 ns ( 55.25 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.425 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.425 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.295 ns) 1.295 ns reset_pin 1 PIN PIN_K2 10 " "Info: 1: + IC(0.000 ns) + CELL(1.295 ns) = 1.295 ns; Loc. = PIN_K2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3459 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.641 ns) + CELL(0.489 ns) 6.425 ns vga_driver:vga_driver_unit\|h_sync 2 REG LC_X34_Y35_N2 3 " "Info: 2: + IC(4.641 ns) + CELL(0.489 ns) = 6.425 ns; Loc. = LC_X34_Y35_N2; Fanout = 3; REG Node = 'vga_driver:vga_driver_unit\|h_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.130 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 153 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.784 ns ( 27.77 % ) " "Info: Total cell delay = 1.784 ns ( 27.77 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.641 ns ( 72.23 % ) " "Info: Total interconnect delay = 4.641 ns ( 72.23 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.425 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.425 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 4.641ns } { 0.000ns 1.295ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.191 ns" { clk_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.191 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 1.763ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.425 ns" { reset_pin vga_driver:vga_driver_unit|h_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.425 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|h_sync {} } { 0.000ns 0.000ns 4.641ns } { 0.000ns 1.295ns 0.489ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "140 " "Info: Peak virtual memory: 140 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:00:52 2009 " "Info: Processing ended: Thu Oct 29 17:00:52 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:01 " "Info: Elapsed time: 00:00:01" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff