4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / sim / db / vga.hif

diff --git a/bsp3/Designflow/ppr/sim/db/vga.hif b/bsp3/Designflow/ppr/sim/db/vga.hif
new file mode 100644 (file)
index 0000000..84411e2
--- /dev/null
+++ b/bsp3/Designflow/ppr/sim/db/vga.hif
@@ -0,0 +1,79 @@
+Version 9.0 Build 132 02/25/2009 SJ Full Version
+45
+3235
+OFF
+OFF
+OFF
+ON
+ON
+ON
+FV_OFF
+Level2
+0
+0
+VRSM_ON
+VHSM_ON
+synplcty.lmf
+-- Start Library Paths --
+-- End Library Paths --
+-- Start VHDL Libraries --
+-- End VHDL Libraries --
+# entity
+vga
+# storage
+db|vga.(0).cnf
+db|vga.(0).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+|
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_driver
+# storage
+db|vga.(1).cnf
+db|vga.(1).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+vga_driver:vga_driver_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# entity
+vga_control
+# storage
+db|vga.(2).cnf
+db|vga.(2).cnf
+# case_sensitive
+# source_file
+..|..|syn|rev_1|vga.vqm
+75b23e99ee7fd7794044e77b9ba64bf9
+28
+# hierarchies {
+vga_control:vga_control_unit
+}
+# lmf
+|opt|quartus|quartus|lmf|synplcty.lmf
+3057712873b497a38b70a3917f30cc38
+# macro_sequence
+
+# end
+# complete
+\r
\ No newline at end of file