--- /dev/null
+# Copyright (C) 1991-2006 Altera Corporation\r
+# Your use of Altera Corporation's design tools, logic functions \r
+# and other software and tools, and its AMPP partner logic \r
+# functions, and any output files any of the foregoing \r
+# (including device programming or simulation files), and any \r
+# associated documentation or information are expressly subject \r
+# to the terms and conditions of the Altera Program License \r
+# Subscription Agreement, Altera MegaCore Function License \r
+# Agreement, or other applicable license agreement, including, \r
+# without limitation, that your use is for the sole purpose of \r
+# programming logic devices manufactured by Altera and sold by \r
+# Altera or its authorized distributors. Please refer to the \r
+# applicable agreement for further details.\r
+\r
+# Quartus II: Generate Tcl File for Project\r
+# File: vga_pll.tcl\r
+# Generated on: Fri Sep 29 09:31:24 2006\r
+\r
+# Load Quartus II Tcl Project package\r
+package require ::quartus::project\r
+package require ::quartus::flow\r
+\r
+set need_to_close_project 0\r
+set make_assignments 1\r
+\r
+# Check that the right project is open\r
+if {[is_project_open]} {\r
+ if {[string compare $quartus(project) "vga_pll"]} {\r
+ puts "Project vga_pll is not open"\r
+ set make_assignments 0\r
+ }\r
+} else {\r
+ # Only open if not already open\r
+ if {[project_exists vga_pll]} {\r
+ project_open -cmp vga_pll vga_pll\r
+ } else {\r
+ project_new -cmp vga_pll vga_pll\r
+ }\r
+ set need_to_close_project 1\r
+}\r
+\r
+# Make assignments\r
+if {$make_assignments} {\r
+ catch { set_global_assignment -name FAMILY Stratix } result\r
+ catch { set_global_assignment -name DEVICE EP1S25F672C6 } result\r
+ catch { set_global_assignment -name ORIGINAL_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name PROJECT_CREATION_TIME_DATE "09:04:10 SEPTEMBER 29, 2006" } result\r
+ catch { set_global_assignment -name LAST_QUARTUS_VERSION 6.0 } result\r
+ catch { set_global_assignment -name EDA_DESIGN_ENTRY_SYNTHESIS_TOOL "Synplify Pro" } result\r
+ catch { set_global_assignment -name EDA_LMF_FILE synplcty.lmf -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_INPUT_DATA_FORMAT VQM -section_id eda_design_synthesis } result\r
+ catch { set_global_assignment -name EDA_SIMULATION_TOOL "ModelSim-Altera (Verilog)" } result\r
+ catch { set_global_assignment -name EDA_TIME_SCALE "1 ps" -section_id eda_simulation } result\r
+ catch { set_global_assignment -name EDA_OUTPUT_DATA_FORMAT VERILOG -section_id eda_simulation } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PACKAGE FBGA } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_PIN_COUNT 672 } result\r
+ catch { set_global_assignment -name DEVICE_FILTER_SPEED_GRADE 6 } result\r
+ catch { set_global_assignment -name BSF_FILE ../../src/vpll.bsf } result\r
+ catch { set_global_assignment -name VHDL_FILE ../../src/vpll.vhd } result\r
+ catch { set_global_assignment -name BDF_FILE ../../src/vga_pll.bdf } result\r
+ catch { set_global_assignment -name VQM_FILE ../../syn/rev_1/vga.vqm } result\r
+\r
+ set_location_assignment PIN_E24 -to b0_pin\r
+ set_location_assignment PIN_T6 -to b1_pin\r
+ set_location_assignment PIN_N3 -to board_clk\r
+ set_location_assignment PIN_E23 -to g0_pin\r
+ set_location_assignment PIN_T5 -to g1_pin\r
+ set_location_assignment PIN_T24 -to g2_pin\r
+ set_location_assignment PIN_F1 -to hsync_pin\r
+ set_location_assignment PIN_E22 -to r0_pin\r
+ set_location_assignment PIN_T4 -to r1_pin\r
+ set_location_assignment PIN_T7 -to r2_pin\r
+ set_location_assignment PIN_A5 -to reset\r
+ set_location_assignment PIN_F2 -to vsync_pin\r
+ set_location_assignment PIN_Y5 -to d_hsync_state[0]\r
+ set_location_assignment PIN_F19 -to d_hsync_state[1]\r
+ set_location_assignment PIN_F17 -to d_hsync_state[2]\r
+ set_location_assignment PIN_Y2 -to d_hsync_state[3]\r
+ set_location_assignment PIN_F10 -to d_hsync_state[4]\r
+ set_location_assignment PIN_F9 -to d_hsync_state[5]\r
+ set_location_assignment PIN_F6 -to d_hsync_state[6]\r
+ set_location_assignment PIN_H4 -to d_hsync_counter[0]\r
+ set_location_assignment PIN_G25 -to d_hsync_counter[7]\r
+ set_location_assignment PIN_G22 -to d_hsync_counter[8]\r
+ set_location_assignment PIN_G18 -to d_hsync_counter[9]\r
+ set_location_assignment PIN_F5 -to d_vsync_state[0]\r
+ set_location_assignment PIN_F4 -to d_vsync_state[1]\r
+ set_location_assignment PIN_F3 -to d_vsync_state[2]\r
+ set_location_assignment PIN_M19 -to d_vsync_state[3]\r
+ set_location_assignment PIN_M18 -to d_vsync_state[4]\r
+ set_location_assignment PIN_M7 -to d_vsync_state[5]\r
+ set_location_assignment PIN_M4 -to d_vsync_state[6]\r
+ set_location_assignment PIN_G9 -to d_vsync_counter[0]\r
+ set_location_assignment PIN_G6 -to d_vsync_counter[7]\r
+ set_location_assignment PIN_G4 -to d_vsync_counter[8]\r
+ set_location_assignment PIN_G2 -to d_vsync_counter[9]\r
+ set_location_assignment PIN_K6 -to d_line_counter[0]\r
+ set_location_assignment PIN_K4 -to d_line_counter[1]\r
+ set_location_assignment PIN_J22 -to d_line_counter[2]\r
+ set_location_assignment PIN_M9 -to d_line_counter[3]\r
+ set_location_assignment PIN_M8 -to d_line_counter[4]\r
+ set_location_assignment PIN_M6 -to d_line_counter[5]\r
+ set_location_assignment PIN_M5 -to d_line_counter[6]\r
+ set_location_assignment PIN_L24 -to d_line_counter[7]\r
+ set_location_assignment PIN_L25 -to d_line_counter[8]\r
+ set_location_assignment PIN_L23 -to d_column_counter[0]\r
+ set_location_assignment PIN_L22 -to d_column_counter[1]\r
+ set_location_assignment PIN_L21 -to d_column_counter[2]\r
+ set_location_assignment PIN_L20 -to d_column_counter[3]\r
+ set_location_assignment PIN_L6 -to d_column_counter[4]\r
+ set_location_assignment PIN_L4 -to d_column_counter[5]\r
+ set_location_assignment PIN_L2 -to d_column_counter[6]\r
+ set_location_assignment PIN_K23 -to d_column_counter[7]\r
+ set_location_assignment PIN_K19 -to d_column_counter[8]\r
+ set_location_assignment PIN_K5 -to d_column_counter[9]\r
+ set_location_assignment PIN_L7 -to d_hsync\r
+ set_location_assignment PIN_L5 -to d_vsync\r
+ set_location_assignment PIN_F26 -to d_set_hsync_counter\r
+ set_location_assignment PIN_F24 -to d_set_vsync_counter\r
+ set_location_assignment PIN_F21 -to d_set_line_counter\r
+ set_location_assignment PIN_Y23 -to d_set_column_counter\r
+ set_location_assignment PIN_L3 -to d_r\r
+ set_location_assignment PIN_K24 -to d_g\r
+ set_location_assignment PIN_K20 -to d_b\r
+ set_location_assignment PIN_H18 -to d_v_enable\r
+ set_location_assignment PIN_J21 -to d_h_enable\r
+ set_location_assignment PIN_R8 -to seven_seg_pin[0]\r
+ set_location_assignment PIN_R9 -to seven_seg_pin[1]\r
+ set_location_assignment PIN_R19 -to seven_seg_pin[2]\r
+ set_location_assignment PIN_R20 -to seven_seg_pin[3]\r
+ set_location_assignment PIN_R21 -to seven_seg_pin[4]\r
+ set_location_assignment PIN_R22 -to seven_seg_pin[5]\r
+ set_location_assignment PIN_R23 -to seven_seg_pin[6]\r
+ set_location_assignment PIN_Y11 -to seven_seg_pin[7]\r
+ set_location_assignment PIN_N7 -to seven_seg_pin[8]\r
+ set_location_assignment PIN_N8 -to seven_seg_pin[9]\r
+ set_location_assignment PIN_R4 -to seven_seg_pin[10]\r
+ set_location_assignment PIN_R6 -to seven_seg_pin[11]\r
+ set_location_assignment PIN_AA11 -to seven_seg_pin[12]\r
+ set_location_assignment PIN_T2 -to seven_seg_pin[13]\r
+ set_location_assignment PIN_K3 -to d_state_clk\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_column_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_hsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_line_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[1]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[2]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[3]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[4]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[5]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_counter[6]\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to d_vsync_state\r
+ set_instance_assignment -name SLOW_SLEW_RATE ON -to seven_seg_pin\r
+\r
+\r
+ # Commit assignments\r
+ export_assignments\r
+\r
+execute_flow -compile\r
+\r
+ # Close project\r
+ if {$need_to_close_project} {\r
+ project_close\r
+ }\r
+}\r
projects / dide_16.git / blobdiff