--- /dev/null
+Analysis & Synthesis report for vga_pll
+Thu Oct 29 17:12:32 2009
+Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
+
+
+---------------------
+; Table of Contents ;
+---------------------
+ 1. Legal Notice
+ 2. Analysis & Synthesis Summary
+ 3. Analysis & Synthesis Settings
+ 4. Analysis & Synthesis Source Files Read
+ 5. Analysis & Synthesis Resource Usage Summary
+ 6. Analysis & Synthesis Resource Utilization by Entity
+ 7. General Register Statistics
+ 8. Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component
+ 9. altpll Parameter Settings by Entity Instance
+ 10. Analysis & Synthesis Messages
+
+
+
+----------------
+; Legal Notice ;
+----------------
+Copyright (C) 1991-2009 Altera Corporation
+Your use of Altera Corporation's design tools, logic functions
+and other software and tools, and its AMPP partner logic
+functions, and any output files from any of the foregoing
+(including device programming or simulation files), and any
+associated documentation or information are expressly subject
+to the terms and conditions of the Altera Program License
+Subscription Agreement, Altera MegaCore Function License
+Agreement, or other applicable license agreement, including,
+without limitation, that your use is for the sole purpose of
+programming logic devices manufactured by Altera and sold by
+Altera or its authorized distributors. Please refer to the
+applicable agreement for further details.
+
+
+
++------------------------------------------------------------------------+
+; Analysis & Synthesis Summary ;
++-----------------------------+------------------------------------------+
+; Analysis & Synthesis Status ; Successful - Thu Oct 29 17:12:32 2009 ;
+; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
+; Revision Name ; vga_pll ;
+; Top-level Entity Name ; vga_pll ;
+; Family ; Stratix ;
+; Total logic elements ; 143 ;
+; Total pins ; 91 ;
+; Total virtual pins ; 0 ;
+; Total memory bits ; 0 ;
+; DSP block 9-bit elements ; 0 ;
+; Total PLLs ; 1 ;
+; Total DLLs ; 0 ;
++-----------------------------+------------------------------------------+
+
+
++----------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Settings ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Option ; Setting ; Default Value ;
++----------------------------------------------------------------+--------------------+--------------------+
+; Device ; EP1S25F672C6 ; ;
+; Top-level entity name ; vga_pll ; vga_pll ;
+; Family name ; Stratix ; Stratix ;
+; Type of Retiming Performed During Resynthesis ; Full ; ;
+; Resynthesis Optimization Effort ; Normal ; ;
+; Physical Synthesis Level for Resynthesis ; Normal ; ;
+; Use Generated Physical Constraints File ; On ; ;
+; Use smart compilation ; Off ; Off ;
+; Restructure Multiplexers ; Auto ; Auto ;
+; Create Debugging Nodes for IP Cores ; Off ; Off ;
+; Preserve fewer node names ; On ; On ;
+; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
+; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
+; VHDL Version ; VHDL93 ; VHDL93 ;
+; State Machine Processing ; Auto ; Auto ;
+; Safe State Machine ; Off ; Off ;
+; Extract Verilog State Machines ; On ; On ;
+; Extract VHDL State Machines ; On ; On ;
+; Ignore Verilog initial constructs ; Off ; Off ;
+; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
+; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
+; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
+; Parallel Synthesis ; Off ; Off ;
+; DSP Block Balancing ; Auto ; Auto ;
+; NOT Gate Push-Back ; On ; On ;
+; Power-Up Don't Care ; On ; On ;
+; Remove Redundant Logic Cells ; Off ; Off ;
+; Remove Duplicate Registers ; On ; On ;
+; Ignore CARRY Buffers ; Off ; Off ;
+; Ignore CASCADE Buffers ; Off ; Off ;
+; Ignore GLOBAL Buffers ; Off ; Off ;
+; Ignore ROW GLOBAL Buffers ; Off ; Off ;
+; Ignore LCELL Buffers ; Off ; Off ;
+; Ignore SOFT Buffers ; On ; On ;
+; Limit AHDL Integers to 32 Bits ; Off ; Off ;
+; Optimization Technique ; Balanced ; Balanced ;
+; Carry Chain Length ; 70 ; 70 ;
+; Auto Carry Chains ; On ; On ;
+; Auto Open-Drain Pins ; On ; On ;
+; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
+; Auto ROM Replacement ; On ; On ;
+; Auto RAM Replacement ; On ; On ;
+; Auto DSP Block Replacement ; On ; On ;
+; Auto Shift Register Replacement ; Auto ; Auto ;
+; Auto Clock Enable Replacement ; On ; On ;
+; Strict RAM Replacement ; Off ; Off ;
+; Allow Synchronous Control Signals ; On ; On ;
+; Force Use of Synchronous Clear Signals ; Off ; Off ;
+; Auto RAM Block Balancing ; On ; On ;
+; Auto RAM to Logic Cell Conversion ; Off ; Off ;
+; Auto Resource Sharing ; Off ; Off ;
+; Allow Any RAM Size For Recognition ; Off ; Off ;
+; Allow Any ROM Size For Recognition ; Off ; Off ;
+; Allow Any Shift Register Size For Recognition ; Off ; Off ;
+; Use LogicLock Constraints during Resource Balancing ; On ; On ;
+; Ignore translate_off and synthesis_off directives ; Off ; Off ;
+; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
+; Synchronization Register Chain Length ; 2 ; 2 ;
+; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
+; HDL message level ; Level2 ; Level2 ;
+; Suppress Register Optimization Related Messages ; Off ; Off ;
+; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
+; Clock MUX Protection ; On ; On ;
+; Block Design Naming ; Auto ; Auto ;
+; Synthesis Effort ; Auto ; Auto ;
+; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
+; Analysis & Synthesis Message Level ; Medium ; Medium ;
++----------------------------------------------------------------+--------------------+--------------------+
+
+
++----------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Source Files Read ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+; ../../src/vga_pll.bdf ; yes ; User Block Diagram/Schematic File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf ;
+; ../../syn/rev_1/vga.vqm ; yes ; User Verilog Quartus Mapping File ; /homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm ;
+; ../../src/vpll.vhd ; yes ; User Wizard-Generated File ; /homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd ;
+; altpll.tdf ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/altpll.tdf ;
+; aglobal90.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/aglobal90.inc ;
+; stratix_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratix_pll.inc ;
+; stratixii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/stratixii_pll.inc ;
+; cycloneii_pll.inc ; yes ; Megafunction ; /opt/quartus/quartus/libraries/megafunctions/cycloneii_pll.inc ;
++----------------------------------+-----------------+------------------------------------+----------------------------------------------------------------+
+
+
++----------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Usage Summary ;
++---------------------------------------------+------------------------------------------+
+; Resource ; Usage ;
++---------------------------------------------+------------------------------------------+
+; Total logic elements ; 143 ;
+; -- Combinational with no register ; 81 ;
+; -- Register only ; 3 ;
+; -- Combinational with a register ; 59 ;
+; ; ;
+; Logic element usage by number of LUT inputs ; ;
+; -- 4 input functions ; 53 ;
+; -- 3 input functions ; 32 ;
+; -- 2 input functions ; 54 ;
+; -- 1 input functions ; 1 ;
+; -- 0 input functions ; 0 ;
+; ; ;
+; Logic elements by mode ; ;
+; -- normal mode ; 109 ;
+; -- arithmetic mode ; 34 ;
+; -- qfbk mode ; 0 ;
+; -- register cascade mode ; 0 ;
+; -- synchronous clear/load mode ; 48 ;
+; -- asynchronous clear/load mode ; 3 ;
+; ; ;
+; Total registers ; 62 ;
+; Total logic cells in carry chains ; 40 ;
+; I/O pins ; 91 ;
+; Total PLLs ; 1 ;
+; Maximum fan-out node ; vpll:inst1|altpll:altpll_component|_clk0 ;
+; Maximum fan-out ; 63 ;
+; Total fan-out ; 667 ;
+; Average fan-out ; 2.84 ;
++---------------------------------------------+------------------------------------------+
+
+
++-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
+; Analysis & Synthesis Resource Utilization by Entity ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+; |vga_pll ; 143 (0) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 91 ; 0 ; 81 (0) ; 3 (0) ; 59 (0) ; 40 (0) ; 0 (0) ; |vga_pll ; work ;
+; |vga:inst| ; 143 (2) ; 62 ; 0 ; 0 ; 0 ; 0 ; 0 ; 90 ; 0 ; 81 (0) ; 3 (0) ; 59 (2) ; 40 (0) ; 0 (0) ; |vga_pll|vga:inst ; work ;
+; |vga_control:vga_control_unit| ; 10 (10) ; 3 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 7 (7) ; 0 (0) ; 3 (3) ; 0 (0) ; 0 (0) ; |vga_pll|vga:inst|vga_control:vga_control_unit ; work ;
+; |vga_driver:vga_driver_unit| ; 131 (131) ; 57 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 74 (74) ; 3 (3) ; 54 (54) ; 40 (40) ; 0 (0) ; |vga_pll|vga:inst|vga_driver:vga_driver_unit ; work ;
+; |vpll:inst1| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1 ; work ;
+; |altpll:altpll_component| ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |vga_pll|vpll:inst1|altpll:altpll_component ; work ;
++--------------------------------------+-------------+--------------+-------------+--------------+---------+-----------+-----------+------+--------------+--------------+-------------------+------------------+-----------------+------------+------------------------------------------------+--------------+
+Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+
+
++------------------------------------------------------+
+; General Register Statistics ;
++----------------------------------------------+-------+
+; Statistic ; Value ;
++----------------------------------------------+-------+
+; Total registers ; 62 ;
+; Number of registers using Synchronous Clear ; 48 ;
+; Number of registers using Synchronous Load ; 20 ;
+; Number of registers using Asynchronous Clear ; 3 ;
+; Number of registers using Asynchronous Load ; 0 ;
+; Number of registers using Clock Enable ; 12 ;
+; Number of registers using Preset ; 0 ;
++----------------------------------------------+-------+
+
+
++---------------------------------------------------------------------------------+
+; Parameter Settings for User Entity Instance: vpll:inst1|altpll:altpll_component ;
++-------------------------------+-------------------+-----------------------------+
+; Parameter Name ; Value ; Type ;
++-------------------------------+-------------------+-----------------------------+
+; OPERATION_MODE ; NORMAL ; Untyped ;
+; PLL_TYPE ; AUTO ; Untyped ;
+; QUALIFY_CONF_DONE ; OFF ; Untyped ;
+; COMPENSATE_CLOCK ; CLK0 ; Untyped ;
+; SCAN_CHAIN ; LONG ; Untyped ;
+; PRIMARY_CLOCK ; INCLK0 ; Untyped ;
+; INCLK0_INPUT_FREQUENCY ; 30003 ; Signed Integer ;
+; INCLK1_INPUT_FREQUENCY ; 0 ; Untyped ;
+; GATE_LOCK_SIGNAL ; NO ; Untyped ;
+; GATE_LOCK_COUNTER ; 0 ; Untyped ;
+; LOCK_HIGH ; 1 ; Untyped ;
+; LOCK_LOW ; 1 ; Untyped ;
+; VALID_LOCK_MULTIPLIER ; 1 ; Signed Integer ;
+; INVALID_LOCK_MULTIPLIER ; 5 ; Signed Integer ;
+; SWITCH_OVER_ON_LOSSCLK ; OFF ; Untyped ;
+; SWITCH_OVER_ON_GATED_LOCK ; OFF ; Untyped ;
+; ENABLE_SWITCH_OVER_COUNTER ; OFF ; Untyped ;
+; SKIP_VCO ; OFF ; Untyped ;
+; SWITCH_OVER_COUNTER ; 0 ; Untyped ;
+; SWITCH_OVER_TYPE ; AUTO ; Untyped ;
+; FEEDBACK_SOURCE ; EXTCLK0 ; Untyped ;
+; BANDWIDTH ; 0 ; Untyped ;
+; BANDWIDTH_TYPE ; AUTO ; Untyped ;
+; SPREAD_FREQUENCY ; 0 ; Signed Integer ;
+; DOWN_SPREAD ; 0 ; Untyped ;
+; SELF_RESET_ON_GATED_LOSS_LOCK ; OFF ; Untyped ;
+; SELF_RESET_ON_LOSS_LOCK ; OFF ; Untyped ;
+; CLK9_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK8_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK7_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK6_MULTIPLY_BY ; 0 ; Untyped ;
+; CLK5_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK4_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; CLK0_MULTIPLY_BY ; 5435 ; Signed Integer ;
+; CLK9_DIVIDE_BY ; 0 ; Untyped ;
+; CLK8_DIVIDE_BY ; 0 ; Untyped ;
+; CLK7_DIVIDE_BY ; 0 ; Untyped ;
+; CLK6_DIVIDE_BY ; 0 ; Untyped ;
+; CLK5_DIVIDE_BY ; 1 ; Untyped ;
+; CLK4_DIVIDE_BY ; 1 ; Untyped ;
+; CLK3_DIVIDE_BY ; 1 ; Untyped ;
+; CLK2_DIVIDE_BY ; 1 ; Untyped ;
+; CLK1_DIVIDE_BY ; 1 ; Untyped ;
+; CLK0_DIVIDE_BY ; 6666 ; Signed Integer ;
+; CLK9_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK8_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK7_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK6_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK4_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; CLK5_TIME_DELAY ; 0 ; Untyped ;
+; CLK4_TIME_DELAY ; 0 ; Untyped ;
+; CLK3_TIME_DELAY ; 0 ; Untyped ;
+; CLK2_TIME_DELAY ; 0 ; Untyped ;
+; CLK1_TIME_DELAY ; 0 ; Untyped ;
+; CLK0_TIME_DELAY ; 0 ; Untyped ;
+; CLK9_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK8_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK7_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK6_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK5_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK4_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; CLK0_DUTY_CYCLE ; 50 ; Signed Integer ;
+; CLK9_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_MODE ; OFF ; Untyped ;
+; CLK9_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK8_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK7_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK6_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK5_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK4_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK3_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK2_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK1_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; CLK0_USE_EVEN_COUNTER_VALUE ; OFF ; Untyped ;
+; LOCK_WINDOW_UI ; 0.05 ; Untyped ;
+; LOCK_WINDOW_UI_BITS ; UNUSED ; Untyped ;
+; VCO_RANGE_DETECTOR_LOW_BITS ; UNUSED ; Untyped ;
+; VCO_RANGE_DETECTOR_HIGH_BITS ; UNUSED ; Untyped ;
+; DPA_MULTIPLY_BY ; 0 ; Untyped ;
+; DPA_DIVIDE_BY ; 1 ; Untyped ;
+; DPA_DIVIDER ; 0 ; Untyped ;
+; EXTCLK3_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK2_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK1_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK0_MULTIPLY_BY ; 1 ; Untyped ;
+; EXTCLK3_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK2_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK1_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK0_DIVIDE_BY ; 1 ; Untyped ;
+; EXTCLK3_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK2_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK1_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK0_PHASE_SHIFT ; 0 ; Untyped ;
+; EXTCLK3_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK2_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK1_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK0_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK2_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK1_DUTY_CYCLE ; 50 ; Untyped ;
+; EXTCLK0_DUTY_CYCLE ; 50 ; Untyped ;
+; VCO_MULTIPLY_BY ; 0 ; Untyped ;
+; VCO_DIVIDE_BY ; 0 ; Untyped ;
+; SCLKOUT0_PHASE_SHIFT ; 0 ; Untyped ;
+; SCLKOUT1_PHASE_SHIFT ; 0 ; Untyped ;
+; VCO_MIN ; 0 ; Untyped ;
+; VCO_MAX ; 0 ; Untyped ;
+; VCO_CENTER ; 0 ; Untyped ;
+; PFD_MIN ; 0 ; Untyped ;
+; PFD_MAX ; 0 ; Untyped ;
+; M_INITIAL ; 0 ; Untyped ;
+; M ; 0 ; Untyped ;
+; N ; 1 ; Untyped ;
+; M2 ; 1 ; Untyped ;
+; N2 ; 1 ; Untyped ;
+; SS ; 1 ; Untyped ;
+; C0_HIGH ; 0 ; Untyped ;
+; C1_HIGH ; 0 ; Untyped ;
+; C2_HIGH ; 0 ; Untyped ;
+; C3_HIGH ; 0 ; Untyped ;
+; C4_HIGH ; 0 ; Untyped ;
+; C5_HIGH ; 0 ; Untyped ;
+; C6_HIGH ; 0 ; Untyped ;
+; C7_HIGH ; 0 ; Untyped ;
+; C8_HIGH ; 0 ; Untyped ;
+; C9_HIGH ; 0 ; Untyped ;
+; C0_LOW ; 0 ; Untyped ;
+; C1_LOW ; 0 ; Untyped ;
+; C2_LOW ; 0 ; Untyped ;
+; C3_LOW ; 0 ; Untyped ;
+; C4_LOW ; 0 ; Untyped ;
+; C5_LOW ; 0 ; Untyped ;
+; C6_LOW ; 0 ; Untyped ;
+; C7_LOW ; 0 ; Untyped ;
+; C8_LOW ; 0 ; Untyped ;
+; C9_LOW ; 0 ; Untyped ;
+; C0_INITIAL ; 0 ; Untyped ;
+; C1_INITIAL ; 0 ; Untyped ;
+; C2_INITIAL ; 0 ; Untyped ;
+; C3_INITIAL ; 0 ; Untyped ;
+; C4_INITIAL ; 0 ; Untyped ;
+; C5_INITIAL ; 0 ; Untyped ;
+; C6_INITIAL ; 0 ; Untyped ;
+; C7_INITIAL ; 0 ; Untyped ;
+; C8_INITIAL ; 0 ; Untyped ;
+; C9_INITIAL ; 0 ; Untyped ;
+; C0_MODE ; BYPASS ; Untyped ;
+; C1_MODE ; BYPASS ; Untyped ;
+; C2_MODE ; BYPASS ; Untyped ;
+; C3_MODE ; BYPASS ; Untyped ;
+; C4_MODE ; BYPASS ; Untyped ;
+; C5_MODE ; BYPASS ; Untyped ;
+; C6_MODE ; BYPASS ; Untyped ;
+; C7_MODE ; BYPASS ; Untyped ;
+; C8_MODE ; BYPASS ; Untyped ;
+; C9_MODE ; BYPASS ; Untyped ;
+; C0_PH ; 0 ; Untyped ;
+; C1_PH ; 0 ; Untyped ;
+; C2_PH ; 0 ; Untyped ;
+; C3_PH ; 0 ; Untyped ;
+; C4_PH ; 0 ; Untyped ;
+; C5_PH ; 0 ; Untyped ;
+; C6_PH ; 0 ; Untyped ;
+; C7_PH ; 0 ; Untyped ;
+; C8_PH ; 0 ; Untyped ;
+; C9_PH ; 0 ; Untyped ;
+; L0_HIGH ; 1 ; Untyped ;
+; L1_HIGH ; 1 ; Untyped ;
+; G0_HIGH ; 1 ; Untyped ;
+; G1_HIGH ; 1 ; Untyped ;
+; G2_HIGH ; 1 ; Untyped ;
+; G3_HIGH ; 1 ; Untyped ;
+; E0_HIGH ; 1 ; Untyped ;
+; E1_HIGH ; 1 ; Untyped ;
+; E2_HIGH ; 1 ; Untyped ;
+; E3_HIGH ; 1 ; Untyped ;
+; L0_LOW ; 1 ; Untyped ;
+; L1_LOW ; 1 ; Untyped ;
+; G0_LOW ; 1 ; Untyped ;
+; G1_LOW ; 1 ; Untyped ;
+; G2_LOW ; 1 ; Untyped ;
+; G3_LOW ; 1 ; Untyped ;
+; E0_LOW ; 1 ; Untyped ;
+; E1_LOW ; 1 ; Untyped ;
+; E2_LOW ; 1 ; Untyped ;
+; E3_LOW ; 1 ; Untyped ;
+; L0_INITIAL ; 1 ; Untyped ;
+; L1_INITIAL ; 1 ; Untyped ;
+; G0_INITIAL ; 1 ; Untyped ;
+; G1_INITIAL ; 1 ; Untyped ;
+; G2_INITIAL ; 1 ; Untyped ;
+; G3_INITIAL ; 1 ; Untyped ;
+; E0_INITIAL ; 1 ; Untyped ;
+; E1_INITIAL ; 1 ; Untyped ;
+; E2_INITIAL ; 1 ; Untyped ;
+; E3_INITIAL ; 1 ; Untyped ;
+; L0_MODE ; BYPASS ; Untyped ;
+; L1_MODE ; BYPASS ; Untyped ;
+; G0_MODE ; BYPASS ; Untyped ;
+; G1_MODE ; BYPASS ; Untyped ;
+; G2_MODE ; BYPASS ; Untyped ;
+; G3_MODE ; BYPASS ; Untyped ;
+; E0_MODE ; BYPASS ; Untyped ;
+; E1_MODE ; BYPASS ; Untyped ;
+; E2_MODE ; BYPASS ; Untyped ;
+; E3_MODE ; BYPASS ; Untyped ;
+; L0_PH ; 0 ; Untyped ;
+; L1_PH ; 0 ; Untyped ;
+; G0_PH ; 0 ; Untyped ;
+; G1_PH ; 0 ; Untyped ;
+; G2_PH ; 0 ; Untyped ;
+; G3_PH ; 0 ; Untyped ;
+; E0_PH ; 0 ; Untyped ;
+; E1_PH ; 0 ; Untyped ;
+; E2_PH ; 0 ; Untyped ;
+; E3_PH ; 0 ; Untyped ;
+; M_PH ; 0 ; Untyped ;
+; C1_USE_CASC_IN ; OFF ; Untyped ;
+; C2_USE_CASC_IN ; OFF ; Untyped ;
+; C3_USE_CASC_IN ; OFF ; Untyped ;
+; C4_USE_CASC_IN ; OFF ; Untyped ;
+; C5_USE_CASC_IN ; OFF ; Untyped ;
+; C6_USE_CASC_IN ; OFF ; Untyped ;
+; C7_USE_CASC_IN ; OFF ; Untyped ;
+; C8_USE_CASC_IN ; OFF ; Untyped ;
+; C9_USE_CASC_IN ; OFF ; Untyped ;
+; CLK0_COUNTER ; G0 ; Untyped ;
+; CLK1_COUNTER ; G0 ; Untyped ;
+; CLK2_COUNTER ; G0 ; Untyped ;
+; CLK3_COUNTER ; G0 ; Untyped ;
+; CLK4_COUNTER ; G0 ; Untyped ;
+; CLK5_COUNTER ; G0 ; Untyped ;
+; CLK6_COUNTER ; E0 ; Untyped ;
+; CLK7_COUNTER ; E1 ; Untyped ;
+; CLK8_COUNTER ; E2 ; Untyped ;
+; CLK9_COUNTER ; E3 ; Untyped ;
+; L0_TIME_DELAY ; 0 ; Untyped ;
+; L1_TIME_DELAY ; 0 ; Untyped ;
+; G0_TIME_DELAY ; 0 ; Untyped ;
+; G1_TIME_DELAY ; 0 ; Untyped ;
+; G2_TIME_DELAY ; 0 ; Untyped ;
+; G3_TIME_DELAY ; 0 ; Untyped ;
+; E0_TIME_DELAY ; 0 ; Untyped ;
+; E1_TIME_DELAY ; 0 ; Untyped ;
+; E2_TIME_DELAY ; 0 ; Untyped ;
+; E3_TIME_DELAY ; 0 ; Untyped ;
+; M_TIME_DELAY ; 0 ; Untyped ;
+; N_TIME_DELAY ; 0 ; Untyped ;
+; EXTCLK3_COUNTER ; E3 ; Untyped ;
+; EXTCLK2_COUNTER ; E2 ; Untyped ;
+; EXTCLK1_COUNTER ; E1 ; Untyped ;
+; EXTCLK0_COUNTER ; E0 ; Untyped ;
+; ENABLE0_COUNTER ; L0 ; Untyped ;
+; ENABLE1_COUNTER ; L0 ; Untyped ;
+; CHARGE_PUMP_CURRENT ; 2 ; Untyped ;
+; LOOP_FILTER_R ; 1.000000 ; Untyped ;
+; LOOP_FILTER_C ; 5 ; Untyped ;
+; CHARGE_PUMP_CURRENT_BITS ; 9999 ; Untyped ;
+; LOOP_FILTER_R_BITS ; 9999 ; Untyped ;
+; LOOP_FILTER_C_BITS ; 9999 ; Untyped ;
+; VCO_POST_SCALE ; 0 ; Untyped ;
+; CLK2_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK1_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; CLK0_OUTPUT_FREQUENCY ; 0 ; Untyped ;
+; INTENDED_DEVICE_FAMILY ; Stratix ; Untyped ;
+; PORT_CLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA4 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKENA5 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLKENA3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_EXTCLK3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKBAD0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKBAD1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK2 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK3 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK4 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK5 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLK6 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK7 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK8 ; PORT_UNUSED ; Untyped ;
+; PORT_CLK9 ; PORT_UNUSED ; Untyped ;
+; PORT_SCANDATA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDATAOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANDONE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCLKOUT0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ACTIVECLOCK ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKLOSS ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_INCLK1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_INCLK0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_FBIN ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PLLENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CLKSWITCH ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ARESET ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PFDENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANCLK ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANACLR ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANREAD ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANWRITE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE0 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_ENABLE1 ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_LOCKED ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_CONFIGUPDATE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_FBOUT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEDONE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASESTEP ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASEUPDOWN ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_SCANCLKENA ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_PHASECOUNTERSELECT ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_VCOOVERRANGE ; PORT_CONNECTIVITY ; Untyped ;
+; PORT_VCOUNDERRANGE ; PORT_CONNECTIVITY ; Untyped ;
+; M_TEST_SOURCE ; 5 ; Untyped ;
+; C0_TEST_SOURCE ; 5 ; Untyped ;
+; C1_TEST_SOURCE ; 5 ; Untyped ;
+; C2_TEST_SOURCE ; 5 ; Untyped ;
+; C3_TEST_SOURCE ; 5 ; Untyped ;
+; C4_TEST_SOURCE ; 5 ; Untyped ;
+; C5_TEST_SOURCE ; 5 ; Untyped ;
+; C6_TEST_SOURCE ; 5 ; Untyped ;
+; C7_TEST_SOURCE ; 5 ; Untyped ;
+; C8_TEST_SOURCE ; 5 ; Untyped ;
+; C9_TEST_SOURCE ; 5 ; Untyped ;
+; CBXI_PARAMETER ; NOTHING ; Untyped ;
+; VCO_FREQUENCY_CONTROL ; AUTO ; Untyped ;
+; VCO_PHASE_SHIFT_STEP ; 0 ; Untyped ;
+; WIDTH_CLOCK ; 6 ; Untyped ;
+; WIDTH_PHASECOUNTERSELECT ; 4 ; Untyped ;
+; USING_FBMIMICBIDIR_PORT ; OFF ; Untyped ;
+; DEVICE_FAMILY ; Stratix ; Untyped ;
+; SCAN_CHAIN_MIF_FILE ; UNUSED ; Untyped ;
+; SIM_GATE_LOCK_DEVICE_BEHAVIOR ; OFF ; Untyped ;
+; AUTO_CARRY_CHAINS ; ON ; AUTO_CARRY ;
+; IGNORE_CARRY_BUFFERS ; OFF ; IGNORE_CARRY ;
+; AUTO_CASCADE_CHAINS ; ON ; AUTO_CASCADE ;
+; IGNORE_CASCADE_BUFFERS ; OFF ; IGNORE_CASCADE ;
++-------------------------------+-------------------+-----------------------------+
+Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
+
+
++--------------------------------------------------------------------+
+; altpll Parameter Settings by Entity Instance ;
++-------------------------------+------------------------------------+
+; Name ; Value ;
++-------------------------------+------------------------------------+
+; Number of entity instances ; 1 ;
+; Entity Instance ; vpll:inst1|altpll:altpll_component ;
+; -- OPERATION_MODE ; NORMAL ;
+; -- PLL_TYPE ; AUTO ;
+; -- PRIMARY_CLOCK ; INCLK0 ;
+; -- INCLK0_INPUT_FREQUENCY ; 30003 ;
+; -- INCLK1_INPUT_FREQUENCY ; 0 ;
+; -- VCO_MULTIPLY_BY ; 0 ;
+; -- VCO_DIVIDE_BY ; 0 ;
++-------------------------------+------------------------------------+
+
+
++-------------------------------+
+; Analysis & Synthesis Messages ;
++-------------------------------+
+Info: *******************************************************************
+Info: Running Quartus II Analysis & Synthesis
+ Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
+ Info: Processing started: Thu Oct 29 17:12:28 2009
+Info: Command: quartus_map --read_settings_files=on --write_settings_files=off vga_pll -c vga_pll
+Info: Revision "vga_pll" was previously opened in Quartus II software version 6.0. Created Quartus II Default Settings File /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll_assignment_defaults.qdf, which contains the default assignment setting information from Quartus II software version 6.0.
+Info: Default assignment values were changed in the current version of the Quartus II software -- changes to default assignments values are contained in file /opt/quartus/quartus/linux/assignment_defaults.qdf
+Info: Found 1 design units, including 1 entities, in source file ../../src/vga_pll.bdf
+ Info: Found entity 1: vga_pll
+Info: Found 3 design units, including 3 entities, in source file ../../syn/rev_1/vga.vqm
+ Info: Found entity 1: vga_driver
+ Info: Found entity 2: vga_control
+ Info: Found entity 3: vga
+Info: Found 2 design units, including 1 entities, in source file ../../src/vpll.vhd
+ Info: Found design unit 1: vpll-SYN
+ Info: Found entity 1: vpll
+Info: Elaborating entity "vga_pll" for the top level hierarchy
+Info: Elaborating entity "vga" for hierarchy "vga:inst"
+Info: Elaborating entity "vga_driver" for hierarchy "vga:inst|vga_driver:vga_driver_unit"
+Info: Elaborating entity "vga_control" for hierarchy "vga:inst|vga_control:vga_control_unit"
+Info: Elaborating entity "vpll" for hierarchy "vpll:inst1"
+Warning (10036): Verilog HDL or VHDL warning at vpll.vhd(73): object "locked" assigned a value but never read
+Info: Elaborating entity "altpll" for hierarchy "vpll:inst1|altpll:altpll_component"
+Info: Elaborated megafunction instantiation "vpll:inst1|altpll:altpll_component"
+Info: Instantiated megafunction "vpll:inst1|altpll:altpll_component" with the following parameter:
+ Info: Parameter "bandwidth_type" = "AUTO"
+ Info: Parameter "clk0_duty_cycle" = "50"
+ Info: Parameter "lpm_type" = "altpll"
+ Info: Parameter "clk0_multiply_by" = "5435"
+ Info: Parameter "invalid_lock_multiplier" = "5"
+ Info: Parameter "inclk0_input_frequency" = "30003"
+ Info: Parameter "gate_lock_signal" = "NO"
+ Info: Parameter "clk0_divide_by" = "6666"
+ Info: Parameter "pll_type" = "AUTO"
+ Info: Parameter "valid_lock_multiplier" = "1"
+ Info: Parameter "clk0_time_delay" = "0"
+ Info: Parameter "spread_frequency" = "0"
+ Info: Parameter "intended_device_family" = "Stratix"
+ Info: Parameter "operation_mode" = "NORMAL"
+ Info: Parameter "compensate_clock" = "CLK0"
+ Info: Parameter "clk0_phase_shift" = "0"
+Info: WYSIWYG I/O primitives converted to equivalent logic
+ Info: WYSIWYG I/O primitive "vga:inst|clk_pin_in" converted to equivalent logic
+Info: Implemented 235 device resources after synthesis - the final resource count might be different
+ Info: Implemented 2 input pins
+ Info: Implemented 89 output pins
+ Info: Implemented 143 logic cells
+ Info: Implemented 1 ClockLock PLLs
+Warning: Output port clk0 of PLL "vpll:inst1|altpll:altpll_component|pll" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance
+Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
+ Info: Peak virtual memory: 204 megabytes
+ Info: Processing ended: Thu Oct 29 17:12:32 2009
+ Info: Elapsed time: 00:00:04
+ Info: Total CPU time (on all processors): 00:00:03
+
+
projects / dide_16.git / blobdiff