4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / download / vga_pll.fit.smsg

diff --git a/bsp3/Designflow/ppr/download/vga_pll.fit.smsg b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg
new file mode 100644 (file)
index 0000000..38de4e4
--- /dev/null
+++ b/bsp3/Designflow/ppr/download/vga_pll.fit.smsg
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+Extra Info: Performing register packing on registers with non-logic cell location assignments
+Extra Info: Completed register packing on registers with non-logic cell location assignments
+Extra Info: Started Fast Input/Output/OE register processing
+Extra Info: Finished Fast Input/Output/OE register processing
+Extra Info: Start inferring scan chains for DSP blocks
+Extra Info: Inferring scan chains for DSP blocks is complete
+Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density
+Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks