--- /dev/null
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions
+// and other software and tools, and its AMPP partner logic
+// functions, and any output files from any of the foregoing
+// (including device programming or simulation files), and any
+// associated documentation or information are expressly subject
+// to the terms and conditions of the Altera Program License
+// Subscription Agreement, Altera MegaCore Function License
+// Agreement, or other applicable license agreement, including,
+// without limitation, that your use is for the sole purpose of
+// programming logic devices manufactured by Altera and sold by
+// Altera or its authorized distributors. Please refer to the
+// applicable agreement for further details.
+
+
+//
+// Device: Altera EP1S25F672C6 Package FBGA672
+//
+
+//
+// This SDF file should be used for ModelSim-Altera (Verilog) only
+//
+
+(DELAYFILE
+ (SDFVERSION "2.1")
+ (DESIGN "vga_pll")
+ (DATE "10/29/2009 17:13:31")
+ (VENDOR "Altera")
+ (PROGRAM "Quartus II")
+ (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+ (DIVIDER .)
+ (TIMESCALE 1 ps)
+
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE board_clk\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (760:760:760) (760:760:760))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_pll")
+ (INSTANCE inst1\|altpll_component\|pll)
+ (DELAY
+ (ABSOLUTE
+ (PORT inclk[0] (649:649:649) (649:649:649))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|reset_pin_in\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (IOPATH padio combout (1141:1141:1141) (1141:1141:1141))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|dly_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5718:5718:5718) (5718:5718:5718))
+ (PORT datac (495:495:495) (495:495:495))
+ (PORT datad (487:487:487) (487:487:487))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|dly_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|dly_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5717:5717:5717) (5717:5717:5717))
+ (PORT datac (498:498:498) (498:498:498))
+ (PORT datad (485:485:485) (485:485:485))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|dly_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5711:5711:5711) (5711:5711:5711))
+ (PORT datac (500:500:500) (500:500:500))
+ (PORT datad (487:487:487) (487:487:487))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (403:403:403) (403:403:403))
+ (PORT datad (2362:2362:2362) (2362:2362:2362))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (493:493:493) (493:493:493))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (423:423:423) (423:423:423))
+ (PORT datac (2734:2734:2734) (2734:2734:2734))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2824:2824:2824) (2824:2824:2824))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (2732:2732:2732) (2732:2732:2732))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2822:2822:2822) (2822:2822:2822))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (2731:2731:2731) (2731:2731:2731))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2821:2821:2821) (2821:2821:2821))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (2730:2730:2730) (2730:2730:2730))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2820:2820:2820) (2820:2820:2820))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (2730:2730:2730) (2730:2730:2730))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2820:2820:2820) (2820:2820:2820))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (2720:2720:2720) (2720:2720:2720))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2810:2810:2810) (2810:2810:2810))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1169:1169:1169) (1169:1169:1169))
+ (PORT datab (1153:1153:1153) (1153:1153:1153))
+ (PORT datac (1176:1176:1176) (1176:1176:1176))
+ (PORT datad (1128:1128:1128) (1128:1128:1128))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (422:422:422) (422:422:422))
+ (PORT datac (2719:2719:2719) (2719:2719:2719))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2809:2809:2809) (2809:2809:2809))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (2722:2722:2722) (2722:2722:2722))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2812:2812:2812) (2812:2812:2812))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (2725:2725:2725) (2725:2725:2725))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2815:2815:2815) (2815:2815:2815))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (2727:2727:2727) (2727:2727:2727))
+ (PORT datad (432:432:432) (432:432:432))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1960:1960:1960) (1960:1960:1960))
+ (PORT datac (2817:2817:2817) (2817:2817:2817))
+ (PORT sclr (1840:1840:1840) (1840:1840:1840))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2102:2102:2102) (2102:2102:2102))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1358:1358:1358) (1358:1358:1358))
+ (PORT datab (1452:1452:1452) (1452:1452:1452))
+ (PORT datac (1397:1397:1397) (1397:1397:1397))
+ (PORT datad (1406:1406:1406) (1406:1406:1406))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1357:1357:1357) (1357:1357:1357))
+ (PORT datab (1173:1173:1173) (1173:1173:1173))
+ (PORT datac (886:886:886) (886:886:886))
+ (PORT datad (340:340:340) (340:340:340))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|G_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2904:2904:2904) (2904:2904:2904))
+ (PORT datab (432:432:432) (432:432:432))
+ (PORT datac (2679:2679:2679) (2679:2679:2679))
+ (PORT datad (253:253:253) (253:253:253))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1184:1184:1184) (1184:1184:1184))
+ (PORT datab (1201:1201:1201) (1201:1201:1201))
+ (PORT datac (1172:1172:1172) (1172:1172:1172))
+ (PORT datad (1150:1150:1150) (1150:1150:1150))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1178:1178:1178) (1178:1178:1178))
+ (PORT datab (1168:1168:1168) (1168:1168:1168))
+ (PORT datac (1157:1157:1157) (1157:1157:1157))
+ (PORT datad (1187:1187:1187) (1187:1187:1187))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1143:1143:1143) (1143:1143:1143))
+ (PORT datab (1153:1153:1153) (1153:1153:1153))
+ (PORT datac (364:364:364) (364:364:364))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1131:1131:1131) (1131:1131:1131))
+ (PORT datac (1167:1167:1167) (1167:1167:1167))
+ (PORT datad (1167:1167:1167) (1167:1167:1167))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1196:1196:1196) (1196:1196:1196))
+ (PORT datab (1207:1207:1207) (1207:1207:1207))
+ (PORT datac (1190:1190:1190) (1190:1190:1190))
+ (PORT datad (1131:1131:1131) (1131:1131:1131))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1192:1192:1192) (1192:1192:1192))
+ (PORT datac (1165:1165:1165) (1165:1165:1165))
+ (PORT datad (1190:1190:1190) (1190:1190:1190))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1197:1197:1197) (1197:1197:1197))
+ (PORT datab (1175:1175:1175) (1175:1175:1175))
+ (PORT datac (1162:1162:1162) (1162:1162:1162))
+ (PORT datad (1144:1144:1144) (1144:1144:1144))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1179:1179:1179) (1179:1179:1179))
+ (PORT datac (1191:1191:1191) (1191:1191:1191))
+ (PORT datad (1133:1133:1133) (1133:1133:1133))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2904:2904:2904) (2904:2904:2904))
+ (PORT datad (436:436:436) (436:436:436))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3448:3448:3448) (3448:3448:3448))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2105:2105:2105) (2105:2105:2105))
+ (PORT ena (1284:1284:1284) (1284:1284:1284))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (357:357:357) (357:357:357))
+ (PORT datab (351:351:351) (351:351:351))
+ (PORT datac (1119:1119:1119) (1119:1119:1119))
+ (PORT datad (359:359:359) (359:359:359))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3460:3460:3460) (3460:3460:3460))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2106:2106:2106) (2106:2106:2106))
+ (PORT ena (1780:1780:1780) (1780:1780:1780))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1093:1093:1093) (1093:1093:1093))
+ (PORT datab (1039:1039:1039) (1039:1039:1039))
+ (PORT datac (1087:1087:1087) (1087:1087:1087))
+ (PORT datad (1200:1200:1200) (1200:1200:1200))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (374:374:374) (374:374:374))
+ (PORT datab (336:336:336) (336:336:336))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (444:444:444) (444:444:444))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3460:3460:3460) (3460:3460:3460))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2106:2106:2106) (2106:2106:2106))
+ (PORT ena (1780:1780:1780) (1780:1780:1780))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (357:357:357) (357:357:357))
+ (PORT datab (951:951:951) (951:951:951))
+ (PORT datac (1401:1401:1401) (1401:1401:1401))
+ (PORT datad (139:139:139) (139:139:139))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1491:1491:1491) (1491:1491:1491))
+ (PORT sclr (3462:3462:3462) (3462:3462:3462))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2105:2105:2105) (2105:2105:2105))
+ (PORT ena (1087:1087:1087) (1087:1087:1087))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1065:1065:1065) (1065:1065:1065))
+ (PORT datab (613:613:613) (613:613:613))
+ (PORT datac (1080:1080:1080) (1080:1080:1080))
+ (PORT datad (1084:1084:1084) (1084:1084:1084))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (360:360:360) (360:360:360))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (2693:2693:2693) (2693:2693:2693))
+ (PORT datad (354:354:354) (354:354:354))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (540:540:540) (540:540:540))
+ (PORT datad (593:593:593) (593:593:593))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3448:3448:3448) (3448:3448:3448))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2105:2105:2105) (2105:2105:2105))
+ (PORT ena (1284:1284:1284) (1284:1284:1284))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (425:425:425) (425:425:425))
+ (PORT datad (554:554:554) (554:554:554))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|hsync_state_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3448:3448:3448) (3448:3448:3448))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2105:2105:2105) (2105:2105:2105))
+ (PORT ena (1284:1284:1284) (1284:1284:1284))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5720:5720:5720) (5720:5720:5720))
+ (PORT datab (479:479:479) (479:479:479))
+ (PORT datac (496:496:496) (496:496:496))
+ (PORT datad (339:339:339) (339:339:339))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1174:1174:1174) (1174:1174:1174))
+ (PORT datab (1140:1140:1140) (1140:1140:1140))
+ (PORT datac (1165:1165:1165) (1165:1165:1165))
+ (PORT datad (1184:1184:1184) (1184:1184:1184))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (360:360:360) (360:360:360))
+ (PORT datab (1168:1168:1168) (1168:1168:1168))
+ (PORT datac (1162:1162:1162) (1162:1162:1162))
+ (PORT datad (595:595:595) (595:595:595))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_hsync_state_3_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2454:2454:2454) (2454:2454:2454))
+ (PORT datad (2798:2798:2798) (2798:2798:2798))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_1_0_0_0_g1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (357:357:357) (357:357:357))
+ (PORT datab (418:418:418) (418:418:418))
+ (PORT datac (2732:2732:2732) (2732:2732:2732))
+ (PORT datad (2505:2505:2505) (2505:2505:2505))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1388:1388:1388) (1388:1388:1388))
+ (PORT datab (4965:4965:4965) (4965:4965:4965))
+ (PORT datac (1402:1402:1402) (1402:1402:1402))
+ (PORT datad (346:346:346) (346:346:346))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|h_sync_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (999:999:999) (999:999:999))
+ (PORT datab (555:555:555) (555:555:555))
+ (PORT datac (1225:1225:1225) (1225:1225:1225))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1315:1315:1315) (1315:1315:1315))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (419:419:419) (419:419:419))
+ (PORT datac (1228:1228:1228) (1228:1228:1228))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1318:1318:1318) (1318:1318:1318))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (444:444:444) (444:444:444))
+ (PORT datac (1231:1231:1231) (1231:1231:1231))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1321:1321:1321) (1321:1321:1321))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datac (1234:1234:1234) (1234:1234:1234))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1324:1324:1324) (1324:1324:1324))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1236:1236:1236) (1236:1236:1236))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout (551:551:551) (551:551:551))
+ (IOPATH cin0 cout (135:135:135) (135:135:135))
+ (IOPATH cin1 cout (123:123:123) (123:123:123))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1326:1326:1326) (1326:1326:1326))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (420:420:420) (420:420:420))
+ (PORT datac (1243:1243:1243) (1243:1243:1243))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1333:1333:1333) (1333:1333:1333))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (416:416:416) (416:416:416))
+ (PORT datac (1242:1242:1242) (1242:1242:1242))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1332:1332:1332) (1332:1332:1332))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (436:436:436) (436:436:436))
+ (PORT datac (1240:1240:1240) (1240:1240:1240))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1330:1330:1330) (1330:1330:1330))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (445:445:445) (445:445:445))
+ (PORT datac (1239:1239:1239) (1239:1239:1239))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1329:1329:1329) (1329:1329:1329))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1234:1234:1234) (1234:1234:1234))
+ (PORT datab (1140:1140:1140) (1140:1140:1140))
+ (PORT datac (1150:1150:1150) (1150:1150:1150))
+ (PORT datad (1248:1248:1248) (1248:1248:1248))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1249:1249:1249) (1249:1249:1249))
+ (PORT datab (1126:1126:1126) (1126:1126:1126))
+ (PORT datac (1214:1214:1214) (1214:1214:1214))
+ (PORT datad (1381:1381:1381) (1381:1381:1381))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1247:1247:1247) (1247:1247:1247))
+ (PORT datab (349:349:349) (349:349:349))
+ (PORT datac (1131:1131:1131) (1131:1131:1131))
+ (PORT datad (348:348:348) (348:348:348))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|G_16.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1461:1461:1461) (1461:1461:1461))
+ (PORT datab (431:431:431) (431:431:431))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (1902:1902:1902) (1902:1902:1902))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1170:1170:1170) (1170:1170:1170))
+ (PORT datab (1183:1183:1183) (1183:1183:1183))
+ (PORT datac (1150:1150:1150) (1150:1150:1150))
+ (PORT datad (1153:1153:1153) (1153:1153:1153))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1204:1204:1204) (1204:1204:1204))
+ (PORT datab (1433:1433:1433) (1433:1433:1433))
+ (PORT datac (1143:1143:1143) (1143:1143:1143))
+ (PORT datad (1475:1475:1475) (1475:1475:1475))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (359:359:359) (359:359:359))
+ (PORT datad (368:368:368) (368:368:368))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (728:728:728) (728:728:728))
+ (PORT datab (682:682:682) (682:682:682))
+ (PORT datac (695:695:695) (695:695:695))
+ (PORT datad (595:595:595) (595:595:595))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (677:677:677) (677:677:677))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (664:664:664) (664:664:664))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1052:1052:1052) (1052:1052:1052))
+ (PORT datab (366:366:366) (366:366:366))
+ (PORT datac (400:400:400) (400:400:400))
+ (PORT datad (1171:1171:1171) (1171:1171:1171))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (907:907:907) (907:907:907))
+ (PORT datab (1230:1230:1230) (1230:1230:1230))
+ (PORT datac (1413:1413:1413) (1413:1413:1413))
+ (PORT datad (1202:1202:1202) (1202:1202:1202))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH qfbkin combout (291:291:291) (291:291:291))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1503:1503:1503) (1503:1503:1503))
+ (PORT sclr (2649:2649:2649) (2649:2649:2649))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (PORT ena (1575:1575:1575) (1575:1575:1575))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1261:1261:1261) (1261:1261:1261))
+ (PORT datab (1126:1126:1126) (1126:1126:1126))
+ (PORT datac (1215:1215:1215) (1215:1215:1215))
+ (PORT datad (1380:1380:1380) (1380:1380:1380))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1244:1244:1244) (1244:1244:1244))
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (1237:1237:1237) (1237:1237:1237))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (360:360:360) (360:360:360))
+ (PORT datac (697:697:697) (697:697:697))
+ (PORT datad (1069:1069:1069) (1069:1069:1069))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (876:876:876) (876:876:876))
+ (PORT datab (359:359:359) (359:359:359))
+ (PORT datac (372:372:372) (372:372:372))
+ (PORT datad (425:425:425) (425:425:425))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (590:590:590) (590:590:590))
+ (PORT datac (1178:1178:1178) (1178:1178:1178))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2648:2648:2648) (2648:2648:2648))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1248:1248:1248) (1248:1248:1248))
+ (PORT datab (570:570:570) (570:570:570))
+ (PORT datac (450:450:450) (450:450:450))
+ (PORT datad (1449:1449:1449) (1449:1449:1449))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (868:868:868) (868:868:868))
+ (PORT datab (1859:1859:1859) (1859:1859:1859))
+ (PORT datac (371:371:371) (371:371:371))
+ (PORT datad (362:362:362) (362:362:362))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1465:1465:1465) (1465:1465:1465))
+ (PORT datab (570:570:570) (570:570:570))
+ (PORT datac (947:947:947) (947:947:947))
+ (PORT datad (1231:1231:1231) (1231:1231:1231))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2648:2648:2648) (2648:2648:2648))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (526:526:526) (526:526:526))
+ (PORT datac (634:634:634) (634:634:634))
+ (PORT datad (344:344:344) (344:344:344))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1917:1917:1917) (1917:1917:1917))
+ (PORT datab (428:428:428) (428:428:428))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (570:570:570) (570:570:570))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|d_set_vsync_counter_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (931:931:931) (931:931:931))
+ (PORT datac (1463:1463:1463) (1463:1463:1463))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1403:1403:1403) (1403:1403:1403))
+ (PORT datab (4962:4962:4962) (4962:4962:4962))
+ (PORT datac (1391:1391:1391) (1391:1391:1391))
+ (PORT datad (873:873:873) (873:873:873))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1238:1238:1238) (1238:1238:1238))
+ (PORT datad (426:426:426) (426:426:426))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ (IOPATH cin regin (607:607:607) (607:607:607))
+ (IOPATH cin0 regin (571:571:571) (571:571:571))
+ (IOPATH cin1 regin (587:587:587) (587:587:587))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_counter_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sload (1966:1966:1966) (1966:1966:1966))
+ (PORT datac (1328:1328:1328) (1328:1328:1328))
+ (PORT sclr (1843:1843:1843) (1843:1843:1843))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2054:2054:2054) (2054:2054:2054))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datac (posedge clk) (10:10:10))
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP sload (posedge clk) (10:10:10))
+ (HOLD datac (posedge clk) (100:100:100))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD sload (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1242:1242:1242) (1242:1242:1242))
+ (PORT datab (570:570:570) (570:570:570))
+ (PORT datac (451:451:451) (451:451:451))
+ (PORT datad (1452:1452:1452) (1452:1452:1452))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|vsync_state_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2648:2648:2648) (2648:2648:2648))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (PORT ena (1086:1086:1086) (1086:1086:1086))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_vsync_state_2_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1414:1414:1414) (1414:1414:1414))
+ (PORT datad (429:429:429) (429:429:429))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_1_0_0_0_g1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (437:437:437) (437:437:437))
+ (PORT datab (996:996:996) (996:996:996))
+ (PORT datac (947:947:947) (947:947:947))
+ (PORT datad (346:346:346) (346:346:346))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1406:1406:1406) (1406:1406:1406))
+ (PORT datab (4964:4964:4964) (4964:4964:4964))
+ (PORT datac (1389:1389:1389) (1389:1389:1389))
+ (PORT datad (553:553:553) (553:553:553))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|v_sync_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5714:5714:5714) (5714:5714:5714))
+ (PORT datab (478:478:478) (478:478:478))
+ (PORT datac (499:499:499) (499:499:499))
+ (PORT datad (2621:2621:2621) (2621:2621:2621))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (417:417:417) (417:417:417))
+ (PORT datad (660:660:660) (660:660:660))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (655:655:655) (655:655:655))
+ (PORT datab (638:638:638) (638:638:638))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (878:878:878) (878:878:878))
+ (PORT datac (408:408:408) (408:408:408))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (461:461:461) (461:461:461))
+ (PORT datab (658:658:658) (658:658:658))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (619:619:619) (619:619:619))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2886:2886:2886) (2886:2886:2886))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1356:1356:1356) (1356:1356:1356))
+ (PORT datab (1127:1127:1127) (1127:1127:1127))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1165:1165:1165) (1165:1165:1165))
+ (PORT datab (1122:1122:1122) (1122:1122:1122))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (411:411:411) (411:411:411))
+ (PORT datad (1072:1072:1072) (1072:1072:1072))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1189:1189:1189) (1189:1189:1189))
+ (PORT datab (1137:1137:1137) (1137:1137:1137))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (415:415:415) (415:415:415))
+ (PORT datad (1045:1045:1045) (1045:1045:1045))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (919:919:919) (919:919:919))
+ (PORT datab (654:654:654) (654:654:654))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (390:390:390) (390:390:390))
+ (PORT datac (554:554:554) (554:554:554))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1219:1219:1219) (1219:1219:1219))
+ (PORT datab (1203:1203:1203) (1203:1203:1203))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (458:458:458) (458:458:458))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (2528:2528:2528) (2528:2528:2528))
+ (PORT datac (1077:1077:1077) (1077:1077:1077))
+ (PORT datad (340:340:340) (340:340:340))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2053:2053:2053) (2053:2053:2053))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_1.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (675:675:675) (675:675:675))
+ (PORT datac (653:653:653) (653:653:653))
+ (PORT datad (427:427:427) (427:427:427))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (438:438:438) (438:438:438))
+ (PORT datab (346:346:346) (346:346:346))
+ (PORT datac (368:368:368) (368:368:368))
+ (PORT datad (626:626:626) (626:626:626))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (458:458:458) (458:458:458))
+ (PORT datab (684:684:684) (684:684:684))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un2_column_counter_next_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1125:1125:1125) (1125:1125:1125))
+ (PORT datad (431:431:431) (431:431:431))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (620:620:620) (620:620:620))
+ (PORT datad (352:352:352) (352:352:352))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_9_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2886:2886:2886) (2886:2886:2886))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1029:1029:1029) (1029:1029:1029))
+ (PORT datab (1364:1364:1364) (1364:1364:1364))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (940:940:940) (940:940:940))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (619:619:619) (619:619:619))
+ (PORT datac (2114:2114:2114) (2114:2114:2114))
+ (PORT datad (361:361:361) (361:361:361))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1077:1077:1077) (1077:1077:1077))
+ (PORT datac (416:416:416) (416:416:416))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|column_counter_sig_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2870:2870:2870) (2870:2870:2870))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_3.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (428:428:428) (428:428:428))
+ (PORT datad (434:434:434) (434:434:434))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_i_o3_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1220:1220:1220) (1220:1220:1220))
+ (PORT datab (1200:1200:1200) (1200:1200:1200))
+ (PORT datac (1156:1156:1156) (1156:1156:1156))
+ (PORT datad (1180:1180:1180) (1180:1180:1180))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|g_next_i_o3_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (657:657:657) (657:657:657))
+ (PORT datad (445:445:445) (445:445:445))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1107:1107:1107) (1107:1107:1107))
+ (PORT datac (2687:2687:2687) (2687:2687:2687))
+ (PORT datad (446:446:446) (446:446:446))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1116:1116:1116) (1116:1116:1116))
+ (PORT datad (435:435:435) (435:435:435))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|v_enable_sig_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (3460:3460:3460) (3460:3460:3460))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2106:2106:2106) (2106:2106:2106))
+ (PORT ena (1096:1096:1096) (1096:1096:1096))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (1863:1863:1863) (1863:1863:1863))
+ (PORT datac (1011:1011:1011) (1011:1011:1011))
+ (PORT datad (902:902:902) (902:902:902))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1885:1885:1885) (1885:1885:1885))
+ (PORT datad (1836:1836:1836) (1836:1836:1836))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|h_enable_sig_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2982:2982:2982) (2982:2982:2982))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2059:2059:2059) (2059:2059:2059))
+ (PORT ena (2543:2543:2543) (2543:2543:2543))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (SETUP ena (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ (HOLD ena (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|r_next_i_o7_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (433:433:433) (433:433:433))
+ (PORT datac (1869:1869:1869) (1869:1869:1869))
+ (PORT datad (2360:2360:2360) (2360:2360:2360))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|N_4_i_0_g0_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (468:468:468) (468:468:468))
+ (PORT datab (1066:1066:1066) (1066:1066:1066))
+ (PORT datac (3037:3037:3037) (3037:3037:3037))
+ (PORT datad (1210:1210:1210) (1210:1210:1210))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|r_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1086:1086:1086) (1086:1086:1086))
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (360:360:360) (360:360:360))
+ (PORT datad (456:456:456) (456:456:456))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|r_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5165:5165:5165) (5165:5165:5165))
+ (PORT clk (2053:2053:2053) (2053:2053:2053))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|N_23_i_0_g0_a_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (538:538:538) (538:538:538))
+ (PORT datab (642:642:642) (642:642:642))
+ (PORT datac (590:590:590) (590:590:590))
+ (PORT datad (912:912:912) (912:912:912))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|g_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1411:1411:1411) (1411:1411:1411))
+ (PORT datab (2777:2777:2777) (2777:2777:2777))
+ (PORT datac (366:366:366) (366:366:366))
+ (PORT datad (1039:1039:1039) (1039:1039:1039))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|g_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5181:5181:5181) (5181:5181:5181))
+ (PORT clk (2040:2040:2040) (2040:2040:2040))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|N_6_i_0_g0_0_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1412:1412:1412) (1412:1412:1412))
+ (PORT datab (2773:2773:2773) (2773:2773:2773))
+ (PORT datac (582:582:582) (582:582:582))
+ (PORT datad (1041:1041:1041) (1041:1041:1041))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_next_i_a7_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (351:351:351) (351:351:351))
+ (PORT datab (652:652:652) (652:652:652))
+ (PORT datac (1154:1154:1154) (1154:1154:1154))
+ (PORT datad (445:445:445) (445:445:445))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_control_unit\|b_Z.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (469:469:469) (469:469:469))
+ (PORT datab (346:346:346) (346:346:346))
+ (PORT datac (1307:1307:1307) (1307:1307:1307))
+ (PORT datad (1121:1121:1121) (1121:1121:1121))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_control_unit\|b_Z.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (5165:5165:5165) (5165:5165:5165))
+ (PORT clk (2053:2053:2053) (2053:2053:2053))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2146:2146:2146) (2146:2146:2146))
+ (PORT datab (1135:1135:1135) (1135:1135:1135))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (5708:5708:5708) (5708:5708:5708))
+ (PORT datab (619:619:619) (619:619:619))
+ (PORT datac (501:501:501) (501:501:501))
+ (PORT datad (488:488:488) (488:488:488))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1062:1062:1062) (1062:1062:1062))
+ (PORT datac (1125:1125:1125) (1125:1125:1125))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_0_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2100:2100:2100) (2100:2100:2100))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1140:1140:1140) (1140:1140:1140))
+ (PORT datab (670:670:670) (670:670:670))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (541:541:541) (541:541:541))
+ (PORT datad (561:561:561) (561:561:561))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_2_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2893:2893:2893) (2893:2893:2893))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2111:2111:2111) (2111:2111:2111))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_a_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (2588:2588:2588) (2588:2588:2588))
+ (PORT datab (422:422:422) (422:422:422))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_2_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (439:439:439) (439:439:439))
+ (PORT datab (1120:1120:1120) (1120:1120:1120))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (344:344:344) (344:344:344))
+ (PORT datac (1123:1123:1123) (1123:1123:1123))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_1_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2100:2100:2100) (2100:2100:2100))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1123:1123:1123) (1123:1123:1123))
+ (PORT datab (424:424:424) (424:424:424))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1126:1126:1126) (1126:1126:1126))
+ (PORT datad (354:354:354) (354:354:354))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_3_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2100:2100:2100) (2100:2100:2100))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (452:452:452) (452:452:452))
+ (PORT datab (1126:1126:1126) (1126:1126:1126))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (367:367:367) (367:367:367))
+ (PORT datad (364:364:364) (364:364:364))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_4_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2691:2691:2691) (2691:2691:2691))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2111:2111:2111) (2111:2111:2111))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (443:443:443) (443:443:443))
+ (PORT datab (1154:1154:1154) (1154:1154:1154))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (359:359:359) (359:359:359))
+ (PORT datab (1864:1864:1864) (1864:1864:1864))
+ (PORT datac (1122:1122:1122) (1122:1122:1122))
+ (IOPATH dataa regin (583:583:583) (583:583:583))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_5_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2100:2100:2100) (2100:2100:2100))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (673:673:673) (673:673:673))
+ (PORT datab (1152:1152:1152) (1152:1152:1152))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ (IOPATH dataa cout0 (443:443:443) (443:443:443))
+ (IOPATH datab cout0 (344:344:344) (344:344:344))
+ (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+ (IOPATH dataa cout1 (451:451:451) (451:451:451))
+ (IOPATH datab cout1 (341:341:341) (341:341:341))
+ (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (537:537:537) (537:537:537))
+ (PORT datad (560:560:560) (560:560:560))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_6_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2893:2893:2893) (2893:2893:2893))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2111:2111:2111) (2111:2111:2111))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (453:453:453) (453:453:453))
+ (PORT datab (1138:1138:1138) (1138:1138:1138))
+ (PORT datac (1145:1145:1145) (1145:1145:1145))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (1139:1139:1139) (1139:1139:1139))
+ (PORT datab (336:336:336) (336:336:336))
+ (PORT datac (1161:1161:1161) (1161:1161:1161))
+ (PORT datad (675:675:675) (675:675:675))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT dataa (670:670:670) (670:670:670))
+ (PORT datab (430:430:430) (430:430:430))
+ (PORT datac (365:365:365) (365:365:365))
+ (PORT datad (1154:1154:1154) (1154:1154:1154))
+ (IOPATH dataa combout (459:459:459) (459:459:459))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datac combout (213:213:213) (213:213:213))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datad (426:426:426) (426:426:426))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datac (1121:1121:1121) (1121:1121:1121))
+ (PORT datad (350:350:350) (350:350:350))
+ (IOPATH datac regin (364:364:364) (364:364:364))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_7_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2653:2653:2653) (2653:2653:2653))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2100:2100:2100) (2100:2100:2100))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|un1_line_counter_sig_9_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (432:432:432) (432:432:432))
+ (PORT datad (1154:1154:1154) (1154:1154:1154))
+ (IOPATH datab combout (332:332:332) (332:332:332))
+ (IOPATH datad combout (87:87:87) (87:87:87))
+ (IOPATH cin0 combout (432:432:432) (432:432:432))
+ (IOPATH cin1 combout (449:449:449) (449:449:449))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_lcell")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lecomb)
+ (DELAY
+ (ABSOLUTE
+ (PORT datab (349:349:349) (349:349:349))
+ (PORT datad (363:363:363) (363:363:363))
+ (IOPATH datab regin (489:489:489) (489:489:489))
+ (IOPATH datad regin (235:235:235) (235:235:235))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_lcell_register")
+ (INSTANCE inst\|vga_driver_unit\|line_counter_sig_8_.lereg)
+ (DELAY
+ (ABSOLUTE
+ (PORT sclr (2691:2691:2691) (2691:2691:2691))
+ (PORT aclr (668:668:668) (668:668:668))
+ (PORT clk (2111:2111:2111) (2111:2111:2111))
+ (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+ (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+ )
+ )
+ (TIMINGCHECK
+ (SETUP datain (posedge clk) (10:10:10))
+ (SETUP sclr (posedge clk) (10:10:10))
+ (HOLD datain (posedge clk) (100:100:100))
+ (HOLD sclr (posedge clk) (100:100:100))
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2877:2877:2877) (2877:2877:2877))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2863:2863:2863) (2863:2863:2863))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_column_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3627:3627:3627) (3627:3627:3627))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_line_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3459:3459:3459) (3459:3459:3459))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_hsync_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3006:3006:3006) (3006:3006:3006))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_set_vsync_counter_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2648:2648:2648) (2648:2648:2648))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_r_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3338:3338:3338) (3338:3338:3338))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_g_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1587:1587:1587) (1587:1587:1587))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_b_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1375:1375:1375) (1375:1375:1375))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_h_enable_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2714:2714:2714) (2714:2714:2714))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_v_enable_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1304:1304:1304) (1304:1304:1304))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_state_clk_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2246:2246:2246) (2246:2246:2246))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2615:2615:2615) (2615:2615:2615))
+ (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3920:3920:3920) (3920:3920:3920))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|r2_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3911:3911:3911) (3911:3911:3911))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2147:2147:2147) (2147:2147:2147))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3965:3965:3965) (3965:3965:3965))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|g2_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2260:2260:2260) (2260:2260:2260))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|b0_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1859:1859:1859) (1859:1859:1859))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|b1_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3616:3616:3616) (3616:3616:3616))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|hsync_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3049:3049:3049) (3049:3049:3049))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|vsync_pin_out\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3155:3155:3155) (3155:3155:3155))
+ (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4366:4366:4366) (4366:4366:4366))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1370:1370:1370) (1370:1370:1370))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1387:1387:1387) (1387:1387:1387))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2873:2873:2873) (2873:2873:2873))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3120:3120:3120) (3120:3120:3120))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3826:3826:3826) (3826:3826:3826))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1359:1359:1359) (1359:1359:1359))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1573:1573:1573) (1573:1573:1573))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1584:1584:1584) (1584:1584:1584))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_column_counter_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1593:1593:1593) (1593:1593:1593))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1730:1730:1730) (1730:1730:1730))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2098:2098:2098) (2098:2098:2098))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1867:1867:1867) (1867:1867:1867))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1365:1365:1365) (1365:1365:1365))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2513:2513:2513) (2513:2513:2513))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1364:1364:1364) (1364:1364:1364))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3133:3133:3133) (3133:3133:3133))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1437:1437:1437) (1437:1437:1437))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4102:4102:4102) (4102:4102:4102))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_counter_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3092:3092:3092) (3092:3092:3092))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4321:4321:4321) (4321:4321:4321))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1660:1660:1660) (1660:1660:1660))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1394:1394:1394) (1394:1394:1394))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (4221:4221:4221) (4221:4221:4221))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2352:2352:2352) (2352:2352:2352))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2640:2640:2640) (2640:2640:2640))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_hsync_state_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2527:2527:2527) (2527:2527:2527))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2083:2083:2083) (2083:2083:2083))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2075:2075:2075) (2075:2075:2075))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3053:3053:3053) (3053:3053:3053))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3100:3100:3100) (3100:3100:3100))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3084:3084:3084) (3084:3084:3084))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3098:3098:3098) (3098:3098:3098))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2427:2427:2427) (2427:2427:2427))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3083:3083:3083) (3083:3083:3083))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_line_counter_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3097:3097:3097) (3097:3097:3097))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3630:3630:3630) (3630:3630:3630))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2885:2885:2885) (2885:2885:2885))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3159:3159:3159) (3159:3159:3159))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3326:3326:3326) (3326:3326:3326))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2901:2901:2901) (2901:2901:2901))
+ (IOPATH datain padio (4488:4488:4488) (4488:4488:4488))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3887:3887:3887) (3887:3887:3887))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2618:2618:2618) (2618:2618:2618))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2170:2170:2170) (2170:2170:2170))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2202:2202:2202) (2202:2202:2202))
+ (IOPATH datain padio (4488:4488:4488) (4488:4488:4488))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_counter_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2481:2481:2481) (2481:2481:2481))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2900:2900:2900) (2900:2900:2900))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2818:2818:2818) (2818:2818:2818))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2675:2675:2675) (2675:2675:2675))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2504:2504:2504) (2504:2504:2504))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2837:2837:2837) (2837:2837:2837))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2841:2841:2841) (2841:2841:2841))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|d_vsync_state_out_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2870:2870:2870) (2870:2870:2870))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_13_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2666:2666:2666) (2666:2666:2666))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_12_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3687:3687:3687) (3687:3687:3687))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_11_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3163:3163:3163) (3163:3163:3163))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_10_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3175:3175:3175) (3175:3175:3175))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_9_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2827:2827:2827) (2827:2827:2827))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_8_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3080:3080:3080) (3080:3080:3080))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_7_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3699:3699:3699) (3699:3699:3699))
+ (IOPATH datain padio (4191:4191:4191) (4191:4191:4191))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_6_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2372:2372:2372) (2372:2372:2372))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_5_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2372:2372:2372) (2372:2372:2372))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_4_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1927:1927:1927) (1927:1927:1927))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_3_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (1927:1927:1927) (1927:1927:1927))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_2_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3112:3112:3112) (3112:3112:3112))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_out_1_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (3163:3163:3163) (3163:3163:3163))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+ (CELL
+ (CELLTYPE "stratix_asynch_io")
+ (INSTANCE inst\|seven_seg_pin_tri_0_\~I.inst1)
+ (DELAY
+ (ABSOLUTE
+ (PORT datain (2003:2003:2003) (2003:2003:2003))
+ (IOPATH datain padio (4100:4100:4100) (4100:4100:4100))
+ )
+ )
+ )
+)
projects / dide_16.git / blobdiff