4er slot (3. bsp fertig)

[dide_16.git] / bsp3 / Designflow / ppr / download / simulation / modelsim / vga_pll.sft

diff --git a/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
new file mode 100644 (file)
index 0000000..5aed62e
--- /dev/null
+++ b/bsp3/Designflow/ppr/download/simulation/modelsim/vga_pll.sft
@@ -0,0 +1,4 @@
+set tool_name "ModelSim-Altera (Verilog)"
+set corner_file_list {
+       {{"Slow Model"} {vga_pll.vo vga_pll_v.sdo}}
+}