--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:13:27 2009 " "Info: Processing started: Thu Oct 29 17:13:27 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_USE_ENABLE_CLOCK_LATENCY_FOR_PLL" "" "Warning: Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" { } { } 0 0 "Clock latency analysis for PLL offsets is supported for the current device family, but is not enabled" 0 0 "" 0 -1}
+{ "Info" "ITAN_SLACK_ANALYSIS" "" "Info: Found timing assignments -- calculating delays" { } { } 0 0 "Found timing assignments -- calculating delays" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 register vga:inst\|vga_control:vga_control_unit\|b 29.381 ns " "Info: Slack time is 29.381 ns for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9\" and destination register \"vga:inst\|vga_control:vga_control_unit\|b\"" { { "Info" "ITDB_SIMPLE_FMAX_RESULT" "135.21 MHz 7.396 ns " "Info: Fmax is 135.21 MHz (period= 7.396 ns)" { } { } 0 0 "Fmax is %1!s! (period= %2!s!)" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.604 ns + Largest register register " "Info: + Largest register to register requirement is 36.604 ns" { { "Info" "ITDB_FULL_SETUP_REQUIREMENT" "36.777 ns + " "Info: + Setup relationship between source and destination is 36.777 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch 35.747 ns " "Info: + Latch edge is 35.747 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Setup relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.013 ns + Largest " "Info: + Largest clock skew is 0.013 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.053 ns + Shortest register " "Info: + Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.053 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.493 ns) + CELL(0.560 ns) 2.053 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG LC_X78_Y32_N4 3 " "Info: 2: + IC(1.493 ns) + CELL(0.560 ns) = 2.053 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.28 % ) " "Info: Total cell delay = 0.560 ns ( 27.28 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.493 ns ( 72.72 % ) " "Info: Total interconnect delay = 1.493 ns ( 72.72 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.040 ns - Longest register " "Info: - Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(0.560 ns) 2.040 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG LC_X78_Y33_N0 4 " "Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.45 % ) " "Info: Total cell delay = 0.560 ns ( 27.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.480 ns ( 72.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns - " "Info: - Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.223 ns - Longest register register " "Info: - Longest register to register delay is 7.223 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG LC_X78_Y33_N0 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X78_Y33_N0; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.360 ns) + CELL(0.087 ns) 2.447 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB LC_X56_Y45_N5 3 " "Info: 2: + IC(2.360 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X56_Y45_N5; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.447 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.773 ns) + CELL(0.332 ns) 5.552 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB LC_X76_Y33_N4 1 " "Info: 3: + IC(2.773 ns) + CELL(0.332 ns) = 5.552 ns; Loc. = LC_X76_Y33_N4; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.105 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.307 ns) + CELL(0.364 ns) 7.223 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG LC_X78_Y32_N4 3 " "Info: 4: + IC(1.307 ns) + CELL(0.364 ns) = 7.223 ns; Loc. = LC_X78_Y32_N4; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.671 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.783 ns ( 10.84 % ) " "Info: Total cell delay = 0.783 ns ( 10.84 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "6.440 ns ( 89.16 % ) " "Info: Total interconnect delay = 6.440 ns ( 89.16 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.053 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 1.493ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.223 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 {} vga:inst|vga_control:vga_control_unit|r_next_i_o7 {} vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 {} vga:inst|vga_control:vga_control_unit|b {} } { 0.000ns 2.360ns 2.773ns 1.307ns } { 0.000ns 0.087ns 0.332ns 0.364ns } "" } } } 0 0 "Slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITAN_NO_REG2REG_EXIST" "board_clk " "Info: No valid register-to-register data paths exist for clock \"board_clk\"" { } { } 0 0 "No valid register-to-register data paths exist for clock \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_MIN_SLACK_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 register vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 737 ps " "Info: Minimum slack time is 737 ps for clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" between source register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\" and destination register \"vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9\"" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.661 ns + Shortest register register " "Info: + Shortest register to register delay is 0.661 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 1 REG LC_X35_Y33_N9 9 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.426 ns) + CELL(0.235 ns) 0.661 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(0.426 ns) + CELL(0.235 ns) = 0.661 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.235 ns ( 35.55 % ) " "Info: Total cell delay = 0.235 ns ( 35.55 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "0.426 ns ( 64.45 % ) " "Info: Total interconnect delay = 0.426 ns ( 64.45 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "-0.076 ns - Smallest register register " "Info: - Smallest register to register requirement is -0.076 ns" { { "Info" "ITDB_FULL_HOLD_REQUIREMENT" "0.000 ns + " "Info: + Hold relationship between source and destination is 0.000 ns" { { "Info" "ITDB_EDGE_RESULT" "+ Latch -1.030 ns " "Info: + Latch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Destination vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Destination clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Setup 1 " "Info: Multicycle Setup factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Destination Hold 1 " "Info: Multicycle Hold factor for Destination register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_EDGE_RESULT" "- Launch -1.030 ns " "Info: - Launch edge is -1.030 ns" { { "Info" "ITDB_CLOCK_SETTING_RESULT" "Source vpll:inst1\|altpll:altpll_component\|_clk0 36.777 ns -1.030 ns 50 " "Info: Clock period of Source clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is 36.777 ns with offset of -1.030 ns and duty cycle of 50" { } { } 0 0 "Clock period of %1!s! clock \"%2!s!\" is %3!s! with %5!s! offset of %4!s! and duty cycle of %6!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Setup 1 " "Info: Multicycle Setup factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} { "Info" "ITDB_MULTICYCLE_RESULT" "Source Hold 1 " "Info: Multicycle Hold factor for Source register is 1" { } { } 0 0 "Multicycle %2!s! factor for %1!s! register is %3!d!" 0 0 "" 0 -1} } { } 0 0 "%1!s! %2!s! edge is %3!s!" 0 0 "" 0 -1} } { } 0 0 "%2!c! Hold relationship between source and destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns + Smallest " "Info: + Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.054 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.054 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9 2 REG LC_X35_Y33_N9 9 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X35_Y33_N9; Fanout = 9; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|vsync_counter_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns - " "Info: - Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 129 25 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "0.661 ns" { vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 0.426ns } { 0.000ns 0.235ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|vsync_counter_9 {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "Minimum slack time is %6!s! for clock \"%1!s!\" between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig reset board_clk 11.030 ns register " "Info: tsu for register \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig\" (data pin = \"reset\", clock pin = \"board_clk\") is 11.030 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "12.049 ns + Longest pin register " "Info: + Longest pin to register delay is 12.049 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.711 ns) + CELL(0.459 ns) 7.311 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.170 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.863 ns) + CELL(0.332 ns) 9.506 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4 3 COMB LC_X34_Y34_N6 1 " "Info: 3: + IC(1.863 ns) + CELL(0.332 ns) = 9.506 ns; Loc. = LC_X34_Y34_N6; Fanout = 1; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.195 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 248 36 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.817 ns) + CELL(0.726 ns) 12.049 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig 4 REG LC_X52_Y35_N2 2 " "Info: 4: + IC(1.817 ns) + CELL(0.726 ns) = 12.049 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.543 ns" { vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.658 ns ( 22.06 % ) " "Info: Total cell delay = 2.658 ns ( 22.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.391 ns ( 77.94 % ) " "Info: Total interconnect delay = 9.391 ns ( 77.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.049 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.049 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 0.000ns 5.711ns 1.863ns 1.817ns } { 0.000ns 1.141ns 0.459ns 0.332ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns - " "Info: - Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.059 ns - Shortest register " "Info: - Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.059 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.499 ns) + CELL(0.560 ns) 2.059 ns vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig 2 REG LC_X52_Y35_N2 2 " "Info: 2: + IC(1.499 ns) + CELL(0.560 ns) = 2.059 ns; Loc. = LC_X52_Y35_N2; Fanout = 2; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.20 % ) " "Info: Total cell delay = 0.560 ns ( 27.20 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.499 ns ( 72.80 % ) " "Info: Total interconnect delay = 1.499 ns ( 72.80 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 1.499ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "12.049 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "12.049 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig_1_0_0_0_g0_i_o4 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 0.000ns 5.711ns 1.863ns 1.817ns } { 0.000ns 1.141ns 0.459ns 0.332ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|h_enable_sig } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.059 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|h_enable_sig {} } { 0.000ns 1.499ns } { 0.000ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "board_clk seven_seg_pin\[7\] vga:inst\|dly_counter\[0\] 9.803 ns register " "Info: tco from clock \"board_clk\" to destination pin \"seven_seg_pin\[7\]\" through register \"vga:inst\|dly_counter\[0\]\" is 9.803 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.054 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.054 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.494 ns) + CELL(0.560 ns) 2.054 ns vga:inst\|dly_counter\[0\] 2 REG LC_X36_Y33_N3 10 " "Info: 2: + IC(1.494 ns) + CELL(0.560 ns) = 2.054 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.26 % ) " "Info: Total cell delay = 0.560 ns ( 27.26 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.494 ns ( 72.74 % ) " "Info: Total interconnect delay = 1.494 ns ( 72.74 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "8.603 ns + Longest register pin " "Info: + Longest register to pin delay is 8.603 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|dly_counter\[0\] 1 REG LC_X36_Y33_N3 10 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X36_Y33_N3; Fanout = 10; REG Node = 'vga:inst\|dly_counter\[0\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|dly_counter[0] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3513 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.500 ns) + CELL(0.213 ns) 0.713 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(0.500 ns) + CELL(0.213 ns) = 0.713 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.713 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.699 ns) + CELL(4.191 ns) 8.603 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 8.603 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.890 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 240 912 1132 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.404 ns ( 51.19 % ) " "Info: Total cell delay = 4.404 ns ( 51.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.199 ns ( 48.81 % ) " "Info: Total interconnect delay = 4.199 ns ( 48.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "8.603 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "8.603 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.500ns 3.699ns } { 0.000ns 0.213ns 4.191ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|dly_counter[0] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.054 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|dly_counter[0] {} } { 0.000ns 1.494ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "8.603 ns" { vga:inst|dly_counter[0] vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "8.603 ns" { vga:inst|dly_counter[0] {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.500ns 3.699ns } { 0.000ns 0.213ns 4.191ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset seven_seg_pin\[7\] 15.201 ns Longest " "Info: Longest tpd from source pin \"reset\" to destination pin \"seven_seg_pin\[7\]\" is 15.201 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.711 ns) + CELL(0.459 ns) 7.311 ns vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X36_Y33_N7 32 " "Info: 2: + IC(5.711 ns) + CELL(0.459 ns) = 7.311 ns; Loc. = LC_X36_Y33_N7; Fanout = 32; COMB Node = 'vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.170 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.699 ns) + CELL(4.191 ns) 15.201 ns seven_seg_pin\[7\] 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.699 ns) + CELL(4.191 ns) = 15.201 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'seven_seg_pin\[7\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.890 ns" { vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 240 912 1132 256 "seven_seg_pin\[13..0\]" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "5.791 ns ( 38.10 % ) " "Info: Total cell delay = 5.791 ns ( 38.10 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "9.410 ns ( 61.90 % ) " "Info: Total interconnect delay = 9.410 ns ( 61.90 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "15.201 ns" { reset vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[7] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "15.201 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[7] {} } { 0.000ns 0.000ns 5.711ns 3.699ns } { 0.000ns 1.141ns 0.459ns 4.191ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "vga:inst\|vga_driver:vga_driver_unit\|v_sync reset board_clk -5.484 ns register " "Info: th for register \"vga:inst\|vga_driver:vga_driver_unit\|v_sync\" (data pin = \"reset\", clock pin = \"board_clk\") is -5.484 ns" { { "Info" "ITDB_FULL_PLL_OFFSET" "board_clk vpll:inst1\|altpll:altpll_component\|_clk0 -1.030 ns + " "Info: + Offset between input clock \"board_clk\" and output clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" is -1.030 ns" { } { { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 80 240 408 96 "board_clk" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! Offset between input clock \"%1!s!\" and output clock \"%2!s!\" is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.040 ns + Longest register " "Info: + Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.040 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.480 ns) + CELL(0.560 ns) 2.040 ns vga:inst\|vga_driver:vga_driver_unit\|v_sync 2 REG LC_X34_Y34_N7 3 " "Info: 2: + IC(1.480 ns) + CELL(0.560 ns) = 2.040 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|v_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 27.45 % ) " "Info: Total cell delay = 0.560 ns ( 27.45 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.480 ns ( 72.55 % ) " "Info: Total interconnect delay = 1.480 ns ( 72.55 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.594 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.594 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.141 ns) 1.141 ns reset 1 PIN PIN_A5 10 " "Info: 1: + IC(0.000 ns) + CELL(1.141 ns) = 1.141 ns; Loc. = PIN_A5; Fanout = 10; PIN Node = 'reset'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset } "NODE_NAME" } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 96 528 696 112 "reset" "" } } } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(4.964 ns) + CELL(0.489 ns) 6.594 ns vga:inst\|vga_driver:vga_driver_unit\|v_sync 2 REG LC_X34_Y34_N7 3 " "Info: 2: + IC(4.964 ns) + CELL(0.489 ns) = 6.594 ns; Loc. = LC_X34_Y34_N7; Fanout = 3; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|v_sync'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.453 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 152 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.630 ns ( 24.72 % ) " "Info: Total cell delay = 1.630 ns ( 24.72 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.964 ns ( 75.28 % ) " "Info: Total interconnect delay = 4.964 ns ( 75.28 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.594 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.594 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 0.000ns 4.964ns } { 0.000ns 1.141ns 0.489ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "2.040 ns" { vpll:inst1|altpll:altpll_component|_clk0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 1.480ns } { 0.000ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.594 ns" { reset vga:inst|vga_driver:vga_driver_unit|v_sync } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.594 ns" { reset {} reset~out0 {} vga:inst|vga_driver:vga_driver_unit|v_sync {} } { 0.000ns 0.000ns 4.964ns } { 0.000ns 1.141ns 0.489ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITAN_REQUIREMENTS_MET_SLOW" "" "Info: All timing requirements were met for slow timing model timing analysis. See Report window for more details." { } { } 0 0 "All timing requirements were met for slow timing model timing analysis. See Report window for more details." 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:27 2009 " "Info: Processing ended: Thu Oct 29 17:13:27 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff