--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Fitter Quartus II " "Info: Running Quartus II Fitter" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Thu Oct 29 17:12:35 2009 " "Info: Processing started: Thu Oct 29 17:12:35 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll " "Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off vga_pll -c vga_pll" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Info" "IMPP_MPP_USER_DEVICE" "vga_pll EP1S25F672C6 " "Info: Selected device EP1S25F672C6 for design \"vga_pll\"" { } { } 0 0 "Selected device %2!s! for design \"%1!s!\"" 0 0 "" 0 -1}
+{ "Warning" "WCUT_CUT_YGR_PLL_BAD_FANOUT_CLK3" "clk0 vpll:inst1\|altpll:altpll_component\|pll " "Warning: Output port clk0 of PLL \"vpll:inst1\|altpll:altpll_component\|pll\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" { } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } } } 0 0 "Output port %1!s! of PLL \"%2!s!\" feeds an output pin via global clocks -- jitter performance depends on switching rate of other design elements. Use PLL dedicated clock outputs to ensure jitter performance" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITCC_INFO_AUTO_FIT_COMPILATION_ON" "" "Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" { } { } 0 0 "Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED" "" "Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" { { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S10F672C6 " "Info: Device EP1S10F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S20F672C6 " "Info: Device EP1S20F672C6 is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_MIGRATION_NOT_SELECTED_SUB" "EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE " "Info: Device EP1S25F672C6_HARDCOPY_FPGA_PROTOTYPE is compatible" { } { } 2 0 "Device %1!s! is compatible" 0 0 "" 0 -1} } { } 2 0 "Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices" 0 0 "" 0 -1}
+{ "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION" "1 " "Info: Fitter converted 1 user pins into dedicated programming pins" { { "Info" "IFIOMGR_RESERVED_PIN_WITH_LOCATION_SUB" "~DATA0~ F16 " "Info: Pin ~DATA0~ is reserved at location F16" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { ~DATA0~ } } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { ~DATA0~ } "NODE_NAME" } } } 0 0 "Pin %1!s! is reserved at location %2!s!" 0 0 "" 0 -1} } { } 0 0 "Fitter converted %1!d! user pins into dedicated programming pins" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_PINS_MISSING_LOCATION_INFO" "12 91 " "Warning: No exact pin location assignment(s) for 12 pins of 91 total pins" { { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[6\] " "Info: Pin d_hsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4076 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[5\] " "Info: Pin d_hsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4089 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[4\] " "Info: Pin d_hsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4102 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[3\] " "Info: Pin d_hsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4115 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[2\] " "Info: Pin d_hsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4128 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_hsync_counter\[1\] " "Info: Pin d_hsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_hsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_hsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4141 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_hsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[6\] " "Info: Pin d_vsync_counter\[6\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3946 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[5\] " "Info: Pin d_vsync_counter\[5\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3959 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[4\] " "Info: Pin d_vsync_counter\[4\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3972 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[3\] " "Info: Pin d_vsync_counter\[3\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3985 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[2\] " "Info: Pin d_vsync_counter\[2\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[2] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[2\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3998 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[2] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} { "Info" "IFIOMGR_PIN_MISSING_LOCATION_INFO" "d_vsync_counter\[1\] " "Info: Pin d_vsync_counter\[1\] not assigned to an exact location on the device" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { d_vsync_counter[1] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "d_vsync_counter\[1\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4011 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { d_vsync_counter[1] } "NODE_NAME" } } } 0 0 "Pin %1!s! not assigned to an exact location on the device" 0 0 "" 0 -1} } { } 0 0 "No exact pin location assignment(s) for %1!d! pins of %2!d! total pins" 0 0 "" 0 -1}
+{ "Info" "ITDC_FITTER_TIMING_ENGINE" "Classic " "Info: Fitter is using the Classic Timing Analyzer" { } { } 0 0 "Fitter is using the %1!s! Timing Analyzer" 0 0 "" 0 -1}
+{ "Info" "ITAN_TDC_USER_OPTIMIZATION_GOALS" "" "Info: Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" { } { } 0 0 "Detected fmax, tsu, tco, and/or tpd requirements -- optimizing circuit to achieve only the specified requirements" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_REG_LOCATION_PROCESSING" "" "Extra Info: Performing register packing on registers with non-logic cell location assignments" { } { } 1 0 "Performing register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_REG_LOCATION_PROCESSING" "" "Extra Info: Completed register packing on registers with non-logic cell location assignments" { } { } 1 0 "Completed register packing on registers with non-logic cell location assignments" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "User Assigned Global Signals Promotion Operation " "Info: Completed User Assigned Global Signals Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "ICUT_CUT_YGR_PLL_CAN_ACHIEVE_RATIO_AND_PHASE_SHIFT" "vpll:inst1\|altpll:altpll_component\|pll " "Info: Implementing parameter values for PLL \"vpll:inst1\|altpll:altpll_component\|pll\"" { { "Info" "ICUT_CUT_YGR_PLL_PARAMETERS_FACTORS" "vpll:inst1\|altpll:altpll_component\|_clk0 31 38 0 -18 " "Info: Implementing clock multiplication of 31, clock division of 38, and phase shift of 0 degrees (-18 ps) for vpll:inst1\|altpll:altpll_component\|_clk0 port" { } { } 0 0 "Implementing clock multiplication of %2!d!, clock division of %3!d!, and phase shift of %4!d! degrees (%5!d! ps) for %1!s! port" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } { "../../src/vpll.vhd" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vpll.vhd" 121 0 0 } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } } } 0 0 "Implementing parameter values for PLL \"%1!s!\"" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_PLL_CLK_PROMOTION" "" "Info: Promoted PLL clock signals" { { "Info" "IFYGR_FYGR_PLL_PROMOTE_GCLK" "vpll:inst1\|altpll:altpll_component\|_clk0 " "Info: Promoted signal \"vpll:inst1\|altpll:altpll_component\|_clk0\" to use global clock" { } { { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "vpll:inst1\|altpll:altpll_component\|_clk0" } } } } { "../../src/vga_pll.bdf" "" { Schematic "/homes/burban/didelu/dide_16/bsp3/Designflow/src/vga_pll.bdf" { { 56 408 504 152 "inst1" "" } } } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 592 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } } 0 0 "Promoted signal \"%1!s!\" to use global clock" 0 0 "" 0 -1} } { } 0 0 "Promoted PLL clock signals" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "PLL Placement Operation " "Info: Completed PLL Placement Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL" "vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x Global clock " "Info: Automatically promoted some destinations of signal \"vga:inst\|vga_driver:vga_driver_unit\|un6_dly_counter_0_x\" to use Global clock" { { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_6_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 118 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_0_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 111 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_1_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 110 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|v_enable_sig_Z\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 155 22 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|h_enable_sig_Z\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 154 22 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_5_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 106 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_4_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_3_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 107 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|vsync_state_2_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 105 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_SUB" "vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_ " "Info: Destination \"vga:inst\|vga_driver:vga_driver_unit\|hsync_state_5_\" may be non-global or may not use global clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 115 23 0 } } } 0 0 "Destination \"%1!s!\" may be non-global or may not use global clock" 0 0 "" 0 -1} { "Info" "IFYGR_FYGR_AUTO_GLOBAL_ASSIGNED_SOME_TO_GLOBAL_LIMITED_TO_SUB" "10 " "Info: Limited to 10 non-global destinations" { } { } 0 0 "Limited to %1!d! non-global destinations" 0 0 "" 0 -1} } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 157 29 0 } } } 0 0 "Automatically promoted some destinations of signal \"%1!s!\" to use %2!s!" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Global Promotion Operation " "Info: Completed Auto Global Promotion Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_START_FYGR_REGPACKING_INFO" "" "Info: Starting register packing" { } { } 0 0 "Starting register packing" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_BEGIN_FAST_REGISTER_INFO" "" "Extra Info: Started Fast Input/Output/OE register processing" { } { } 1 0 "Started Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_FAST_REGISTER_INFO" "" "Extra Info: Finished Fast Input/Output/OE register processing" { } { } 1 0 "Finished Fast Input/Output/OE register processing" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Start inferring scan chains for DSP blocks" { } { } 1 0 "Start inferring scan chains for DSP blocks" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_MAC_SCAN_CHAIN_INFERENCING" "" "Extra Info: Inferring scan chains for DSP blocks is complete" { } { } 1 0 "Inferring scan chains for DSP blocks is complete" 1 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_INFO_AUTO_MODE_REGISTER_PACKING" "Auto Normal " "Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option" { } { } 0 0 "Fitter is using %2!s! packing mode for logic elements with %1!s! setting for Auto Packed Registers logic option" 0 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_START_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" { } { } 1 0 "Moving registers into I/O cells, LUTs, RAM blocks, and DSP blocks to improve timing and density" 1 0 "" 0 -1}
+{ "Extra Info" "IFSAC_FSAC_FINISH_LUT_IO_MAC_RAM_PACKING" "" "Extra Info: Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" { } { } 1 0 "Finished moving registers into LUTs, I/O cells, DSP blocks, and RAM blocks" 1 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" { } { } 0 0 "Finished register packing" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "12 unused 3.3V 0 12 0 " "Info: Number of I/O pins in group: 12 (unused VREF, 3.3V VCCIO, 0 input, 12 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "3.3-V LVTTL. " "Info: I/O standards used: 3.3-V LVTTL." { } { } 0 0 "I/O standards used: %1!s!" 0 0 "" 0 -1} } { } 0 0 "Number of I/O pins in group: %1!d! (%2!s! VREF, %3!s! VCCIO, %4!d! input, %5!d! output, %6!d! bidirectional)" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.3V 11 50 " "Info: I/O bank number 1 does not use VREF pins and has 3.3V VCCIO pins. 11 total pin(s) used -- 50 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use 3.3V 27 32 " "Info: I/O bank number 2 does not use VREF pins and has 3.3V VCCIO pins. 27 total pin(s) used -- 32 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "3 does not use 3.3V 6 48 " "Info: I/O bank number 3 does not use VREF pins and has 3.3V VCCIO pins. 6 total pin(s) used -- 48 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "4 does not use 3.3V 7 49 " "Info: I/O bank number 4 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 49 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "5 does not use 3.3V 20 39 " "Info: I/O bank number 5 does not use VREF pins and has 3.3V VCCIO pins. 20 total pin(s) used -- 39 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "6 does not use 3.3V 7 54 " "Info: I/O bank number 6 does not use VREF pins and has 3.3V VCCIO pins. 7 total pin(s) used -- 54 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "7 does not use undetermined 0 57 " "Info: I/O bank number 7 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 57 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "8 does not use 3.3V 2 52 " "Info: I/O bank number 8 does not use VREF pins and has 3.3V VCCIO pins. 2 total pin(s) used -- 52 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "9 does not use undetermined 0 6 " "Info: I/O bank number 9 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "11 does not use undetermined 0 6 " "Info: I/O bank number 11 does not use VREF pins and has undetermined VCCIO pins. 0 total pin(s) used -- 6 pins available" { } { } 0 0 "I/O bank number %1!s! %2!s! VREF pins and has %3!s! VCCIO pins. %4!d! total pin(s) used -- %5!d! pins available" 0 0 "" 0 -1} } { } 0 0 "Statistics of %1!s!" 0 0 "" 0 -1} } { } 0 0 "I/O bank details %1!s! I/O pin placement" 0 0 "" 0 -1}
+{ "Info" "IFITCC_FITTER_PREPARATION_END" "00:00:03 " "Info: Fitter preparation operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" { } { } 0 0 "Fitter placement preparation operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" { } { } 0 0 "Fitter placement preparation operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" { } { } 0 0 "Fitter placement operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" { } { } 0 0 "Fitter placement was successful" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:03 " "Info: Fitter placement operations ending: elapsed time is 00:00:03" { } { } 0 0 "Fitter placement operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_SLACK_TPD_RESULT" "register vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 register vga:inst\|vga_control:vga_control_unit\|b 29.931 ns " "Info: Slack time is 29.931 ns between source register \"vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9\" and destination register \"vga:inst\|vga_control:vga_control_unit\|b\"" { { "Info" "ITDB_FULL_P2P_REQUIREMENT_RESULT" "36.591 ns + Largest register register " "Info: + Largest register to register requirement is 36.591 ns" { } { } 0 0 "%2!c! %3!s! %4!s! to %5!s! requirement is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns Shortest register " "Info: Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG Unassigned 3 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 destination 2.138 ns Longest register " "Info: Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to destination register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_control:vga_control_unit\|b 2 REG Unassigned 3 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns Shortest register " "Info: Shortest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "vpll:inst1\|altpll:altpll_component\|_clk0 source 2.138 ns Longest register " "Info: Longest clock path from clock \"vpll:inst1\|altpll:altpll_component\|_clk0\" to source register is 2.138 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vpll:inst1\|altpll:altpll_component\|_clk0 1 CLK PLL_1 63 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = PLL_1; Fanout = 63; CLK Node = 'vpll:inst1\|altpll:altpll_component\|_clk0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vpll:inst1|altpll:altpll_component|_clk0 } "NODE_NAME" } } { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.578 ns) + CELL(0.560 ns) 2.138 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 2 REG Unassigned 4 " "Info: 2: + IC(1.578 ns) + CELL(0.560 ns) = 2.138 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.138 ns" { vpll:inst1|altpll:altpll_component|_clk0 vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.560 ns ( 26.19 % ) " "Info: Total cell delay = 0.560 ns ( 26.19 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.578 ns ( 73.81 % ) " "Info: Total interconnect delay = 1.578 ns ( 73.81 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "altpll.tdf" "" { Text "/opt/quartus/quartus/libraries/megafunctions/altpll.tdf" 905 3 0 } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns " "Info: Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns " "Info: Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.660 ns - Longest register register " "Info: - Longest register to register delay is 6.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG Unassigned 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = Unassigned; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.459 ns) 2.567 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB Unassigned 3 " "Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = Unassigned; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.567 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.405 ns) + CELL(0.087 ns) 5.059 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB Unassigned 1 " "Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = Unassigned; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.492 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.235 ns) 6.660 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG Unassigned 3 " "Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = Unassigned; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.601 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.781 ns ( 11.73 % ) " "Info: Total cell delay = 0.781 ns ( 11.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.879 ns ( 88.27 % ) " "Info: Total interconnect delay = 5.879 ns ( 88.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } } 0 0 "Slack time is %5!s! between source %1!s! \"%2!s!\" and destination %3!s! \"%4!s!\"" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.660 ns register register " "Info: Estimated most critical path is register to register delay of 6.660 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9 1 REG LAB_X78_Y33 4 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X78_Y33; Fanout = 4; REG Node = 'vga:inst\|vga_driver:vga_driver_unit\|column_counter_sig_9'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 128 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.108 ns) + CELL(0.459 ns) 2.567 ns vga:inst\|vga_control:vga_control_unit\|r_next_i_o7 2 COMB LAB_X56_Y45 3 " "Info: 2: + IC(2.108 ns) + CELL(0.459 ns) = 2.567 ns; Loc. = LAB_X56_Y45; Fanout = 3; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|r_next_i_o7'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.567 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3207 19 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(2.405 ns) + CELL(0.087 ns) 5.059 ns vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0 3 COMB LAB_X76_Y33 1 " "Info: 3: + IC(2.405 ns) + CELL(0.087 ns) = 5.059 ns; Loc. = LAB_X76_Y33; Fanout = 1; COMB Node = 'vga:inst\|vga_control:vga_control_unit\|N_6_i_0_g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.492 ns" { vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3205 20 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.366 ns) + CELL(0.235 ns) 6.660 ns vga:inst\|vga_control:vga_control_unit\|b 4 REG LAB_X78_Y32 3 " "Info: 4: + IC(1.366 ns) + CELL(0.235 ns) = 6.660 ns; Loc. = LAB_X78_Y32; Fanout = 3; REG Node = 'vga:inst\|vga_control:vga_control_unit\|b'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.601 ns" { vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 3185 11 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.781 ns ( 11.73 % ) " "Info: Total cell delay = 0.781 ns ( 11.73 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.879 ns ( 88.27 % ) " "Info: Total interconnect delay = 5.879 ns ( 88.27 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.660 ns" { vga:inst|vga_driver:vga_driver_unit|column_counter_sig_9 vga:inst|vga_control:vga_control_unit|r_next_i_o7 vga:inst|vga_control:vga_control_unit|N_6_i_0_g0_0 vga:inst|vga_control:vga_control_unit|b } "NODE_NAME" } } } 0 0 "Estimated most critical path is %2!s! to %3!s! delay of %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" { } { } 0 0 "Fitter routing operations beginning" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_PERCENT_ROUTING_RESOURCE_USAGE" "0 " "Info: Average interconnect usage is 0% of the available device resources" { { "Info" "IFITAPI_FITAPI_VPR_PEAK_ROUTING_REGION" "1 X34_Y24 X44_Y35 " "Info: Peak interconnect usage is 1% of the available device resources in the region that extends from location X34_Y24 to location X44_Y35" { } { } 0 0 "Peak interconnect usage is %1!d!%% of the available device resources in the region that extends from location %2!s! to location %3!s!" 0 0 "" 0 -1} } { } 0 0 "Average interconnect usage is %1!d!%% of the available device resources" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:01 " "Info: Fitter routing operations ending: elapsed time is 00:00:01" { } { } 0 0 "Fitter routing operations ending: elapsed time is %1!s!" 0 0 "" 0 -1}
+{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED" "" "Info: The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." { { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_ROUTABILITY" "" "Info: Optimizations that may affect the design's routability were skipped" { } { } 0 0 "Optimizations that may affect the design's routability were skipped" 0 0 "" 0 -1} { "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_USED_FOR_TIMING" "" "Info: Optimizations that may affect the design's timing were skipped" { } { } 0 0 "Optimizations that may affect the design's timing were skipped" 0 0 "" 0 -1} } { } 0 0 "The Fitter performed an Auto Fit compilation. Optimizations were skipped to reduce compilation time." 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Fixed Delay Chain Operation " "Info: Completed Fixed Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_STARTED" "" "Info: Started post-fitting delay annotation" { } { } 0 0 "Started post-fitting delay annotation" 0 0 "" 0 -1}
+{ "Info" "IDAT_DAT_COMPLETED" "" "Info: Delay annotation completed successfully" { } { } 0 0 "Delay annotation completed successfully" 0 0 "" 0 -1}
+{ "Info" "IFYGR_FYGR_OPINFO_COMPLETED_OP" "Auto Delay Chain Operation " "Info: Completed Auto Delay Chain Operation" { } { } 0 0 "Completed %1!s!" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN" "6 " "Warning: Following 6 pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" { { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[13\] GND " "Info: Pin seven_seg_pin\[13\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[13] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[13\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4466 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[13] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[6\] GND " "Info: Pin seven_seg_pin\[6\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[6] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[6\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4557 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[6] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[5\] GND " "Info: Pin seven_seg_pin\[5\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[5] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[5\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4570 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[5] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[4\] GND " "Info: Pin seven_seg_pin\[4\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[4] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[4\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4583 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[4] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[3\] GND " "Info: Pin seven_seg_pin\[3\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[3] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[3\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4596 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[3] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} { "Info" "IFIOMGR_BIDIR_OR_OUTPUT_WITH_TRIVIAL_DATAIN_SUB" "seven_seg_pin\[0\] GND " "Info: Pin seven_seg_pin\[0\] has GND driving its datain port" { } { { "/opt/quartus/quartus/linux/pin_planner.ppl" "" { PinPlanner "/opt/quartus/quartus/linux/pin_planner.ppl" { seven_seg_pin[0] } } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "seven_seg_pin\[0\]" } } } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp3/Designflow/syn/rev_1/vga.vqm" 4635 3 0 } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { seven_seg_pin[0] } "NODE_NAME" } } } 0 0 "Pin %1!s! has %2!s! driving its datain port" 0 0 "" 0 -1} } { } 0 0 "Following %1!d! pins have nothing, GND, or VCC driving datain port -- changes to this connectivity may change fitting results" 0 0 "" 0 -1}
+{ "Warning" "WFIOMGR_RESERVE_ASSIGNMENT_FOR_UNUSED_PINS_IS_DEFAULT" "As output driving ground " "Warning: The Reserve All Unused Pins setting has not been specified, and will default to 'As output driving ground'." { } { } 0 0 "The Reserve All Unused Pins setting has not been specified, and will default to '%1!s!'." 0 0 "" 0 -1}
+{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "/homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg " "Info: Generated suppressed messages file /homes/burban/didelu/dide_16/bsp3/Designflow/ppr/download/vga_pll.fit.smsg" { } { } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 4 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 4 warnings" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "320 " "Info: Peak virtual memory: 320 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Thu Oct 29 17:13:03 2009 " "Info: Processing ended: Thu Oct 29 17:13:03 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:28 " "Info: Elapsed time: 00:00:28" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:28 " "Info: Total CPU time (on all processors): 00:00:28" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff