dritter slot

[dide_16.git] / bsp2 / Designflow / ppr / sim / simulation / modelsim / vga_vhd.sdo

diff --git a/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo b/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo
new file mode 100644 (file)
index 0000000..d313c49
--- /dev/null
+++ b/bsp2/Designflow/ppr/sim/simulation/modelsim/vga_vhd.sdo
@@ -0,0 +1,5593 @@
+// Copyright (C) 1991-2009 Altera Corporation
+// Your use of Altera Corporation's design tools, logic functions 
+// and other software and tools, and its AMPP partner logic 
+// functions, and any output files from any of the foregoing 
+// (including device programming or simulation files), and any 
+// associated documentation or information are expressly subject 
+// to the terms and conditions of the Altera Program License 
+// Subscription Agreement, Altera MegaCore Function License 
+// Agreement, or other applicable license agreement, including, 
+// without limitation, that your use is for the sole purpose of 
+// programming logic devices manufactured by Altera and sold by 
+// Altera or its authorized distributors.  Please refer to the 
+// applicable agreement for further details.
+
+
+// 
+// Device: Altera EP1S25F672C6 Package FBGA672
+// 
+
+// 
+// This SDF file should be used for ModelSim (VHDL) only
+// 
+
+(DELAYFILE
+  (SDFVERSION "2.1")
+  (DESIGN "vga")
+  (DATE "10/28/2009 14:19:55")
+  (VENDOR "Altera")
+  (PROGRAM "Quartus II")
+  (VERSION "Version 9.0 Build 132 02/25/2009 SJ Full Version")
+  (DIVIDER .)
+  (TIMESCALE 1 ps)
+
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE clk_pin_in.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (868:868:868) (868:868:868))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE reset_pin_in.inst1)
+    (DELAY
+      (ABSOLUTE
+        (IOPATH padio combout (760:760:760) (760:760:760))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\dly_counter_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1030:1030:1030) (1030:1030:1030))
+        (PORT datac (5264:5264:5264) (5264:5264:5264))
+        (PORT datad (447:447:447) (447:447:447))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\dly_counter_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\dly_counter_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1107:1107:1107) (1107:1107:1107))
+        (PORT datab (2654:2654:2654) (2654:2654:2654))
+        (PORT datac (5010:5010:5010) (5010:5010:5010))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\dly_counter_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (427:427:427) (427:427:427))
+        (PORT datac (5016:5016:5016) (5016:5016:5016))
+        (PORT datad (1088:1088:1088) (1088:1088:1088))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1535:1535:1535) (1535:1535:1535))
+        (PORT datad (1150:1150:1150) (1150:1150:1150))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1625:1625:1625) (1625:1625:1625))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (423:423:423) (423:423:423))
+        (PORT datac (1506:1506:1506) (1506:1506:1506))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1596:1596:1596) (1596:1596:1596))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (1505:1505:1505) (1505:1505:1505))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1595:1595:1595) (1595:1595:1595))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (1503:1503:1503) (1503:1503:1503))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1593:1593:1593) (1593:1593:1593))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (1506:1506:1506) (1506:1506:1506))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1596:1596:1596) (1596:1596:1596))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1509:1509:1509) (1509:1509:1509))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1599:1599:1599) (1599:1599:1599))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (1516:1516:1516) (1516:1516:1516))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1606:1606:1606) (1606:1606:1606))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (422:422:422) (422:422:422))
+        (PORT datac (1514:1514:1514) (1514:1514:1514))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1604:1604:1604) (1604:1604:1604))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (1513:1513:1513) (1513:1513:1513))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_7_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1603:1603:1603) (1603:1603:1603))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (1513:1513:1513) (1513:1513:1513))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_8_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1603:1603:1603) (1603:1603:1603))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1512:1512:1512) (1512:1512:1512))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_9_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1602:1602:1602) (1602:1602:1602))
+        (PORT sclr (1861:1861:1861) (1861:1861:1861))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (663:663:663) (663:663:663))
+        (PORT datab (608:608:608) (608:608:608))
+        (PORT datac (653:653:653) (653:653:653))
+        (PORT datad (986:986:986) (986:986:986))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_7\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (638:638:638) (638:638:638))
+        (PORT datab (591:591:591) (591:591:591))
+        (PORT datac (641:641:641) (641:641:641))
+        (PORT datad (641:641:641) (641:641:641))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_COUNT_next_un9_hsync_counterlt9\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (975:975:975) (975:975:975))
+        (PORT datab (624:624:624) (624:624:624))
+        (PORT datac (366:366:366) (366:366:366))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|G_2\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (447:447:447))
+        (PORT datab (1613:1613:1613) (1613:1613:1613))
+        (PORT datac (1074:1074:1074) (1074:1074:1074))
+        (PORT datad (1479:1479:1479) (1479:1479:1479))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter_2\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (662:662:662) (662:662:662))
+        (PORT datab (626:626:626) (626:626:626))
+        (PORT datac (970:970:970) (970:970:970))
+        (PORT datad (991:991:991) (991:991:991))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un13_hsync_counter\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (924:924:924) (924:924:924))
+        (PORT datab (609:609:609) (609:609:609))
+        (PORT datac (370:370:370) (370:370:370))
+        (PORT datad (351:351:351) (351:351:351))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (936:936:936) (936:936:936))
+        (PORT datab (924:924:924) (924:924:924))
+        (PORT datac (922:922:922) (922:922:922))
+        (PORT datad (923:923:923) (923:923:923))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un11_hsync_counter_2\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (927:927:927) (927:927:927))
+        (PORT datac (921:921:921) (921:921:921))
+        (PORT datad (938:938:938) (938:938:938))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_1\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (990:990:990) (990:990:990))
+        (PORT datac (1013:1013:1013) (1013:1013:1013))
+        (PORT datad (1020:1020:1020) (1020:1020:1020))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (447:447:447) (447:447:447))
+        (PORT datac (1641:1641:1641) (1641:1641:1641))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2555:2555:2555) (2555:2555:2555))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2387:2387:2387) (2387:2387:2387))
+        (PORT ena (1796:1796:1796) (1796:1796:1796))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (922:922:922) (922:922:922))
+        (PORT datab (927:927:927) (927:927:927))
+        (PORT datac (958:958:958) (958:958:958))
+        (PORT datad (925:925:925) (925:925:925))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un10_hsync_counter_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (926:926:926) (926:926:926))
+        (PORT datac (924:924:924) (924:924:924))
+        (PORT datad (938:938:938) (938:938:938))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1226:1226:1226) (1226:1226:1226))
+        (PORT datab (856:856:856) (856:856:856))
+        (PORT datac (1030:1030:1030) (1030:1030:1030))
+        (PORT datad (856:856:856) (856:856:856))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2570:2570:2570) (2570:2570:2570))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (PORT ena (1299:1299:1299) (1299:1299:1299))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (565:565:565) (565:565:565))
+        (PORT datab (565:565:565) (565:565:565))
+        (PORT datac (1029:1029:1029) (1029:1029:1029))
+        (PORT datad (440:440:440) (440:440:440))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2570:2570:2570) (2570:2570:2570))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (PORT ena (1299:1299:1299) (1299:1299:1299))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (984:984:984) (984:984:984))
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (1016:1016:1016) (1016:1016:1016))
+        (PORT datad (353:353:353) (353:353:353))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1106:1106:1106) (1106:1106:1106))
+        (PORT sclr (2308:2308:2308) (2308:2308:2308))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (PORT ena (1091:1091:1091) (1091:1091:1091))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1228:1228:1228) (1228:1228:1228))
+        (PORT datab (547:547:547) (547:547:547))
+        (PORT datac (552:552:552) (552:552:552))
+        (PORT datad (1038:1038:1038) (1038:1038:1038))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (638:638:638) (638:638:638))
+        (PORT datab (560:560:560) (560:560:560))
+        (PORT datac (367:367:367) (367:367:367))
+        (PORT datad (1041:1041:1041) (1041:1041:1041))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_3_0_0_0__g0_0_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1544:1544:1544) (1544:1544:1544))
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (562:562:562) (562:562:562))
+        (PORT datad (544:544:544) (544:544:544))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1051:1051:1051) (1051:1051:1051))
+        (PORT datac (1129:1129:1129) (1129:1129:1129))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2555:2555:2555) (2555:2555:2555))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2387:2387:2387) (2387:2387:2387))
+        (PORT ena (1796:1796:1796) (1796:1796:1796))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (5249:5249:5249) (5249:5249:5249))
+        (PORT datab (1448:1448:1448) (1448:1448:1448))
+        (PORT datac (1232:1232:1232) (1232:1232:1232))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (654:654:654) (654:654:654))
+        (PORT datab (622:622:622) (622:622:622))
+        (PORT datac (623:623:623) (623:623:623))
+        (PORT datad (642:642:642) (642:642:642))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (667:667:667) (667:667:667))
+        (PORT datab (592:592:592) (592:592:592))
+        (PORT datac (971:971:971) (971:971:971))
+        (PORT datad (986:986:986) (986:986:986))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|HSYNC_FSM_next_un12_hsync_counter\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (638:638:638) (638:638:638))
+        (PORT datab (624:624:624) (624:624:624))
+        (PORT datac (369:369:369) (369:369:369))
+        (PORT datad (351:351:351) (351:351:351))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (951:951:951) (951:951:951))
+        (PORT datac (561:561:561) (561:561:561))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|hsync_state_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2570:2570:2570) (2570:2570:2570))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (PORT ena (1299:1299:1299) (1299:1299:1299))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|v_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (435:435:435) (435:435:435))
+        (PORT datac (1220:1220:1220) (1220:1220:1220))
+        (PORT datad (1534:1534:1534) (1534:1534:1534))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1196:1196:1196) (1196:1196:1196))
+        (PORT datac (1173:1173:1173) (1173:1173:1173))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|v_enable_sig_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2271:2271:2271) (2271:2271:2271))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2359:2359:2359) (2359:2359:2359))
+        (PORT ena (1824:1824:1824) (1824:1824:1824))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (441:441:441) (441:441:441))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1149:1149:1149) (1149:1149:1149))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (607:607:607) (607:607:607))
+        (PORT datab (423:423:423) (423:423:423))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (939:939:939) (939:939:939))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|un2_toggle_counter_next_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (618:618:618) (618:618:618))
+        (PORT datab (906:906:906) (906:906:906))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (634:634:634) (634:634:634))
+        (PORT datab (889:889:889) (889:889:889))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1348:1348:1348) (1348:1348:1348))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (429:429:429) (429:429:429))
+        (PORT datab (963:963:963) (963:963:963))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1348:1348:1348) (1348:1348:1348))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datab (894:894:894) (894:894:894))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datab (928:928:928) (928:928:928))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_7_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (432:432:432) (432:432:432))
+        (PORT datab (908:908:908) (908:908:908))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1348:1348:1348) (1348:1348:1348))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (947:947:947))
+        (PORT datab (413:413:413) (413:413:413))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (644:644:644) (644:644:644))
+        (IOPATH datab cout (533:533:533) (533:533:533))
+        (IOPATH cin0 cout (219:219:219) (219:219:219))
+        (IOPATH cin1 cout (205:205:205) (205:205:205))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_8_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1348:1348:1348) (1348:1348:1348))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (922:922:922) (922:922:922))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_9_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1371:1371:1371) (1371:1371:1371))
+        (PORT datab (420:420:420) (420:420:420))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_11_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (607:607:607) (607:607:607))
+        (PORT datab (1355:1355:1355) (1355:1355:1355))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_10_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1364:1364:1364) (1364:1364:1364))
+        (PORT datab (422:422:422) (422:422:422))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_13_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1362:1362:1362) (1362:1362:1362))
+        (PORT datab (419:419:419) (419:419:419))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_12_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datab (1360:1360:1360) (1360:1360:1360))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_15_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (438:438:438) (438:438:438))
+        (PORT datab (1368:1368:1368) (1368:1368:1368))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_14_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1370:1370:1370) (1370:1370:1370))
+        (PORT datab (957:957:957) (957:957:957))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_16_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datab (1406:1406:1406) (1406:1406:1406))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_17_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1393:1393:1393) (1393:1393:1393))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_19_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1319:1319:1319) (1319:1319:1319))
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (439:439:439) (439:439:439))
+        (PORT datab (1365:1365:1365) (1365:1365:1365))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (628:628:628) (628:628:628))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH datab cout (460:460:460) (460:460:460))
+        (IOPATH cin cout (110:110:110) (110:110:110))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_18_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_20_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_counter_sig_20_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1852:1852:1852) (1852:1852:1852))
+        (PORT aclr (5079:5079:5079) (5079:5079:5079))
+        (PORT clk (2336:2336:2336) (2336:2336:2336))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglt6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (581:581:581) (581:581:581))
+        (PORT datad (599:599:599) (599:599:599))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto9\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (605:605:605) (605:605:605))
+        (PORT datab (578:578:578) (578:578:578))
+        (PORT datac (595:595:595) (595:595:595))
+        (PORT datad (363:363:363) (363:363:363))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto12\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (651:651:651) (651:651:651))
+        (PORT datab (1098:1098:1098) (1098:1098:1098))
+        (PORT datac (1137:1137:1137) (1137:1137:1137))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto15\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1111:1111:1111) (1111:1111:1111))
+        (PORT datab (622:622:622) (622:622:622))
+        (PORT datac (679:679:679) (679:679:679))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|BLINKER_next_un1_toggle_counter_siglto18\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1201:1201:1201) (1201:1201:1201))
+        (PORT datab (623:623:623) (623:623:623))
+        (PORT datac (1397:1397:1397) (1397:1397:1397))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_sig_0_0_0_g1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1137:1137:1137) (1137:1137:1137))
+        (PORT datab (635:635:635) (635:635:635))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (438:438:438) (438:438:438))
+        (PORT datad (348:348:348) (348:348:348))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|toggle_sig_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (657:657:657) (657:657:657))
+        (PORT datab (1630:1630:1630) (1630:1630:1630))
+        (PORT datac (692:692:692) (692:692:692))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (782:782:782) (782:782:782))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (419:419:419) (419:419:419))
+        (PORT datac (696:696:696) (696:696:696))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (786:786:786) (786:786:786))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (444:444:444) (444:444:444))
+        (PORT datac (699:699:699) (699:699:699))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (789:789:789) (789:789:789))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (437:437:437) (437:437:437))
+        (PORT datac (702:702:702) (702:702:702))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (792:792:792) (792:792:792))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (704:704:704) (704:704:704))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout (551:551:551) (551:551:551))
+        (IOPATH cin0 cout (135:135:135) (135:135:135))
+        (IOPATH cin1 cout (123:123:123) (123:123:123))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (794:794:794) (794:794:794))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (420:420:420) (420:420:420))
+        (PORT datac (709:709:709) (709:709:709))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (799:799:799) (799:799:799))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (628:628:628) (628:628:628))
+        (PORT datab (611:611:611) (611:611:611))
+        (PORT datac (623:623:623) (623:623:623))
+        (PORT datad (937:937:937) (937:937:937))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (416:416:416) (416:416:416))
+        (PORT datac (709:709:709) (709:709:709))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (799:799:799) (799:799:799))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (436:436:436) (436:436:436))
+        (PORT datac (708:708:708) (708:708:708))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_7_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (798:798:798) (798:798:798))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (445:445:445) (445:445:445))
+        (PORT datac (708:708:708) (708:708:708))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_8_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (798:798:798) (798:798:798))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (706:706:706) (706:706:706))
+        (PORT datad (426:426:426) (426:426:426))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+        (IOPATH cin regin (607:607:607) (607:607:607))
+        (IOPATH cin0 regin (571:571:571) (571:571:571))
+        (IOPATH cin1 regin (587:587:587) (587:587:587))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_9_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sload (1434:1434:1434) (1434:1434:1434))
+        (PORT datac (796:796:796) (796:796:796))
+        (PORT sclr (1316:1316:1316) (1316:1316:1316))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP sload (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD sload (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9_5\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (616:616:616) (616:616:616))
+        (PORT datab (607:607:607) (607:607:607))
+        (PORT datac (925:925:925) (925:925:925))
+        (PORT datad (958:958:958) (958:958:958))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_COUNT_next_un9_vsync_counterlt9\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (630:630:630))
+        (PORT datab (348:348:348) (348:348:348))
+        (PORT datac (934:934:934) (934:934:934))
+        (PORT datad (352:352:352) (352:352:352))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|G_16\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (994:994:994) (994:994:994))
+        (PORT datab (945:945:945) (945:945:945))
+        (PORT datac (1070:1070:1070) (1070:1070:1070))
+        (PORT datad (353:353:353) (353:353:353))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (673:673:673) (673:673:673))
+        (PORT datad (438:438:438) (438:438:438))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1153:1153:1153) (1153:1153:1153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (PORT ena (1287:1287:1287) (1287:1287:1287))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (634:634:634) (634:634:634))
+        (PORT datab (601:601:601) (601:601:601))
+        (PORT datac (932:932:932) (932:932:932))
+        (PORT datad (643:643:643) (643:643:643))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un14_vsync_counter_8\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (377:377:377) (377:377:377))
+        (PORT datad (360:360:360) (360:360:360))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (687:687:687) (687:687:687))
+        (PORT datab (662:662:662) (662:662:662))
+        (PORT datac (993:993:993) (993:993:993))
+        (PORT datad (361:361:361) (361:361:361))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (688:688:688) (688:688:688))
+        (PORT datab (662:662:662) (662:662:662))
+        (PORT datac (1270:1270:1270) (1270:1270:1270))
+        (PORT datad (361:361:361) (361:361:361))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH qfbkin combout (291:291:291) (291:291:291))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1360:1360:1360) (1360:1360:1360))
+        (PORT sclr (1885:1885:1885) (1885:1885:1885))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (PORT ena (1091:1091:1091) (1091:1091:1091))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+        (IOPATH (posedge clk) qfbkout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) qfbkout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datac (posedge clk) (10:10:10))
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datac (posedge clk) (100:100:100))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (976:976:976) (976:976:976))
+        (PORT datab (990:990:990) (990:990:990))
+        (PORT datac (1023:1023:1023) (1023:1023:1023))
+        (PORT datad (576:576:576) (576:576:576))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1153:1153:1153) (1153:1153:1153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (PORT ena (1287:1287:1287) (1287:1287:1287))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (630:630:630) (630:630:630))
+        (PORT datab (621:621:621) (621:621:621))
+        (PORT datac (624:624:624) (624:624:624))
+        (PORT datad (622:622:622) (622:622:622))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un15_vsync_counter_4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (930:930:930) (930:930:930))
+        (PORT datac (608:608:608) (608:608:608))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1037:1037:1037) (1037:1037:1037))
+        (PORT datab (987:987:987) (987:987:987))
+        (PORT datac (1025:1025:1025) (1025:1025:1025))
+        (PORT datad (575:575:575) (575:575:575))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1153:1153:1153) (1153:1153:1153))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (PORT ena (1287:1287:1287) (1287:1287:1287))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (657:657:657) (657:657:657))
+        (PORT datab (604:604:604) (604:604:604))
+        (PORT datac (683:683:683) (683:683:683))
+        (PORT datad (633:633:633) (633:633:633))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un13_vsync_counter_4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (639:639:639) (639:639:639))
+        (PORT datac (995:995:995) (995:995:995))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_next_1_sqmuxa_2_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (708:708:708) (708:708:708))
+        (PORT datac (370:370:370) (370:370:370))
+        (PORT datad (360:360:360) (360:360:360))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_vsync_state_next_1_sqmuxa_0_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (369:369:369) (369:369:369))
+        (PORT datab (934:934:934) (934:934:934))
+        (PORT datac (874:874:874) (874:874:874))
+        (PORT datad (348:348:348) (348:348:348))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_next_2_sqmuxa_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1116:1116:1116) (1116:1116:1116))
+        (PORT datab (341:341:341) (341:341:341))
+        (PORT datac (371:371:371) (371:371:371))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_3_iv_0_0__g0_0_a3_0_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (432:432:432) (432:432:432))
+        (PORT datac (877:877:877) (877:877:877))
+        (PORT datad (555:555:555) (555:555:555))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (366:366:366) (366:366:366))
+        (PORT datab (430:430:430) (430:430:430))
+        (PORT datac (571:571:571) (571:571:571))
+        (PORT datad (846:846:846) (846:846:846))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|d_set_vsync_counter_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (944:944:944) (944:944:944))
+        (PORT datad (983:983:983) (983:983:983))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_counter_next_1_sqmuxa_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (363:363:363) (363:363:363))
+        (PORT datab (2412:2412:2412) (2412:2412:2412))
+        (PORT datac (5264:5264:5264) (5264:5264:5264))
+        (PORT datad (451:451:451) (451:451:451))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|VSYNC_FSM_next_un12_vsync_counter_7\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (613:613:613) (613:613:613))
+        (PORT datab (626:626:626) (626:626:626))
+        (PORT datac (623:623:623) (623:623:623))
+        (PORT datad (644:644:644) (644:644:644))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1202:1202:1202) (1202:1202:1202))
+        (PORT datab (1172:1172:1172) (1172:1172:1172))
+        (PORT datac (2469:2469:2469) (2469:2469:2469))
+        (PORT datad (2008:2008:2008) (2008:2008:2008))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|vsync_state_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (5244:5244:5244) (5244:5244:5244))
+        (PORT datab (1216:1216:1216) (1216:1216:1216))
+        (PORT datac (1151:1151:1151) (1151:1151:1151))
+        (PORT datad (1419:1419:1419) (1419:1419:1419))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1160:1160:1160) (1160:1160:1160))
+        (PORT datab (935:935:935) (935:935:935))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (608:608:608) (608:608:608))
+        (PORT datad (851:851:851) (851:851:851))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1996:1996:1996) (1996:1996:1996))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_a_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (658:658:658) (658:658:658))
+        (PORT datab (951:951:951) (951:951:951))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (692:692:692) (692:692:692))
+        (PORT datab (685:685:685) (685:685:685))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (519:519:519) (519:519:519))
+        (PORT datac (601:601:601) (601:601:601))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1996:1996:1996) (1996:1996:1996))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (990:990:990) (990:990:990))
+        (PORT datab (999:999:999) (999:999:999))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (602:602:602) (602:602:602))
+        (PORT datad (846:846:846) (846:846:846))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1996:1996:1996) (1996:1996:1996))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (663:663:663) (663:663:663))
+        (PORT datab (645:645:645) (645:645:645))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (611:611:611) (611:611:611))
+        (PORT datac (540:540:540) (540:540:540))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1996:1996:1996) (1996:1996:1996))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (947:947:947) (947:947:947))
+        (PORT datab (875:875:875) (875:875:875))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (601:601:601) (601:601:601))
+        (PORT datad (341:341:341) (341:341:341))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1703:1703:1703) (1703:1703:1703))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1042:1042:1042) (1042:1042:1042))
+        (PORT datab (666:666:666) (666:666:666))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (354:354:354) (354:354:354))
+        (PORT datac (1110:1110:1110) (1110:1110:1110))
+        (PORT datad (1100:1100:1100) (1100:1100:1100))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1036:1036:1036) (1036:1036:1036))
+        (PORT datab (593:593:593) (593:593:593))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (360:360:360) (360:360:360))
+        (PORT datad (609:609:609) (609:609:609))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1703:1703:1703) (1703:1703:1703))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (718:718:718) (718:718:718))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (553:553:553) (553:553:553))
+        (PORT datad (610:610:610) (610:610:610))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_7_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1703:1703:1703) (1703:1703:1703))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglt4_2\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (433:433:433) (433:433:433))
+        (PORT datac (444:444:444) (444:444:444))
+        (PORT datad (971:971:971) (971:971:971))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto5\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (989:989:989) (989:989:989))
+        (PORT datab (999:999:999) (999:999:999))
+        (PORT datac (868:868:868) (868:868:868))
+        (PORT datad (1026:1026:1026) (1026:1026:1026))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|LINE_COUNT_next_un10_line_counter_siglto8\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (625:625:625) (625:625:625))
+        (PORT datab (670:670:670) (670:670:670))
+        (PORT datac (735:735:735) (735:735:735))
+        (PORT datad (555:555:555) (555:555:555))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_line_counter_sig_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (416:416:416) (416:416:416))
+        (PORT datad (420:420:420) (420:420:420))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (602:602:602) (602:602:602))
+        (PORT datad (253:253:253) (253:253:253))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|line_counter_sig_8_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (1703:1703:1703) (1703:1703:1703))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2369:2369:2369) (2369:2369:2369))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un17_v_enablelto3\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (662:662:662) (662:662:662))
+        (PORT datab (685:685:685) (685:685:685))
+        (PORT datac (944:944:944) (944:944:944))
+        (PORT datad (675:675:675) (675:675:675))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_4_a_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (667:667:667) (667:667:667))
+        (PORT datab (671:671:671) (671:671:671))
+        (PORT datac (364:364:364) (364:364:364))
+        (PORT datad (1028:1028:1028) (1028:1028:1028))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto4_0\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (417:417:417) (417:417:417))
+        (PORT datad (970:970:970) (970:970:970))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un13_v_enablelto6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1038:1038:1038) (1038:1038:1038))
+        (PORT datab (651:651:651) (651:651:651))
+        (PORT datac (689:689:689) (689:689:689))
+        (PORT datad (558:558:558) (558:558:558))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_4_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (626:626:626) (626:626:626))
+        (PORT datab (721:721:721) (721:721:721))
+        (PORT datac (359:359:359) (359:359:359))
+        (PORT datad (340:340:340) (340:340:340))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_next_0_sqmuxa_1_1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1383:1383:1383) (1383:1383:1383))
+        (PORT datab (1010:1010:1010) (1010:1010:1010))
+        (PORT datac (5258:5258:5258) (5258:5258:5258))
+        (PORT datad (455:455:455) (455:455:455))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (441:441:441) (441:441:441))
+        (PORT datad (1121:1121:1121) (1121:1121:1121))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_0_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2276:2276:2276) (2276:2276:2276))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1142:1142:1142) (1142:1142:1142))
+        (PORT datab (1099:1099:1099) (1099:1099:1099))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1088:1088:1088) (1088:1088:1088))
+        (PORT datad (1118:1118:1118) (1118:1118:1118))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_1_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2276:2276:2276) (2276:2276:2276))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1183:1183:1183) (1183:1183:1183))
+        (PORT datab (1161:1161:1161) (1161:1161:1161))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (1068:1068:1068) (1068:1068:1068))
+        (PORT datad (1153:1153:1153) (1153:1153:1153))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_3_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2266:2266:2266) (2266:2266:2266))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_0_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (651:651:651) (651:651:651))
+        (PORT datab (626:626:626) (626:626:626))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (450:450:450))
+        (PORT datab (989:989:989) (989:989:989))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (336:336:336) (336:336:336))
+        (PORT datad (1150:1150:1150) (1150:1150:1150))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_2_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2266:2266:2266) (2266:2266:2266))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (448:448:448) (448:448:448))
+        (PORT datab (1111:1111:1111) (1111:1111:1111))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (351:351:351) (351:351:351))
+        (PORT datac (1102:1102:1102) (1102:1102:1102))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_5_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2252:2252:2252) (2252:2252:2252))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2319:2319:2319) (2319:2319:2319))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (720:720:720) (720:720:720))
+        (PORT datab (1119:1119:1119) (1119:1119:1119))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (362:362:362) (362:362:362))
+        (PORT datad (1154:1154:1154) (1154:1154:1154))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_4_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2266:2266:2266) (2266:2266:2266))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (639:639:639) (639:639:639))
+        (PORT datab (1135:1135:1135) (1135:1135:1135))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datad (585:585:585) (585:585:585))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1513:1513:1513) (1513:1513:1513))
+        (PORT datac (549:549:549) (549:549:549))
+        (PORT datad (1118:1118:1118) (1118:1118:1118))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_8_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6_4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1173:1173:1173) (1173:1173:1173))
+        (PORT datab (1101:1101:1101) (1101:1101:1101))
+        (PORT datac (1118:1118:1118) (1118:1118:1118))
+        (PORT datad (1129:1129:1129) (1129:1129:1129))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglt6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (448:448:448) (448:448:448))
+        (PORT datab (1108:1108:1108) (1108:1108:1108))
+        (PORT datac (1146:1146:1146) (1146:1146:1146))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1153:1153:1153) (1153:1153:1153))
+        (PORT datab (417:417:417) (417:417:417))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+        (IOPATH dataa cout0 (443:443:443) (443:443:443))
+        (IOPATH datab cout0 (344:344:344) (344:344:344))
+        (IOPATH cin0 cout0 (60:60:60) (60:60:60))
+        (IOPATH dataa cout1 (451:451:451) (451:451:451))
+        (IOPATH datab cout1 (341:341:341) (341:341:341))
+        (IOPATH cin1 cout1 (62:62:62) (62:62:62))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un2_column_counter_next_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1224:1224:1224) (1224:1224:1224))
+        (PORT datab (422:422:422) (422:422:422))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH cin0 combout (432:432:432) (432:432:432))
+        (IOPATH cin1 combout (449:449:449) (449:449:449))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (343:343:343) (343:343:343))
+        (PORT datac (1106:1106:1106) (1106:1106:1106))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_9_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2252:2252:2252) (2252:2252:2252))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2319:2319:2319) (2319:2319:2319))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|COLUMN_COUNT_next_un10_column_counter_siglto9\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (2428:2428:2428) (2428:2428:2428))
+        (PORT datab (1196:1196:1196) (1196:1196:1196))
+        (PORT datac (1094:1094:1094) (1094:1094:1094))
+        (PORT datad (1196:1196:1196) (1196:1196:1196))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1469:1469:1469) (1469:1469:1469))
+        (PORT datac (1105:1105:1105) (1105:1105:1105))
+        (PORT datad (354:354:354) (354:354:354))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_7_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2319:2319:2319) (2319:2319:2319))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (367:367:367) (367:367:367))
+        (PORT datad (1154:1154:1154) (1154:1154:1154))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|column_counter_sig_6_\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2266:2266:2266) (2266:2266:2266))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2311:2311:2311) (2311:2311:2311))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelt2\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (450:450:450) (450:450:450))
+        (PORT datab (630:630:630) (630:630:630))
+        (PORT datad (639:639:639) (639:639:639))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un5_v_enablelto5\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1075:1075:1075) (1075:1075:1075))
+        (PORT datab (1222:1222:1222) (1222:1222:1222))
+        (PORT datac (1189:1189:1189) (1189:1189:1189))
+        (PORT datad (1403:1403:1403) (1403:1403:1403))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|h_enable_sig_1_0_0_0_g0_i_o4_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (1917:1917:1917) (1917:1917:1917))
+        (PORT datac (1598:1598:1598) (1598:1598:1598))
+        (PORT datad (1966:1966:1966) (1966:1966:1966))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datac (443:443:443) (443:443:443))
+        (PORT datad (1589:1589:1589) (1589:1589:1589))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|h_enable_sig_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT sclr (2747:2747:2747) (2747:2747:2747))
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (PORT ena (1082:1082:1082) (1082:1082:1082))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (SETUP sclr (posedge clk) (10:10:10))
+      (SETUP ena (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+      (HOLD sclr (posedge clk) (100:100:100))
+      (HOLD ena (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_2_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1512:1512:1512) (1512:1512:1512))
+        (PORT datab (424:424:424) (424:424:424))
+        (PORT datac (1409:1409:1409) (1409:1409:1409))
+        (PORT datad (1197:1197:1197) (1197:1197:1197))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto4\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1178:1178:1178) (1178:1178:1178))
+        (PORT datac (1169:1169:1169) (1169:1169:1169))
+        (PORT datad (1226:1226:1226) (1226:1226:1226))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|DRAW_SQUARE_next_un9_v_enablelto6\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1141:1141:1141) (1141:1141:1141))
+        (PORT datab (1168:1168:1168) (1168:1168:1168))
+        (PORT datad (354:354:354) (354:354:354))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_3_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1206:1206:1206) (1206:1206:1206))
+        (PORT datab (347:347:347) (347:347:347))
+        (PORT datac (1216:1216:1216) (1216:1216:1216))
+        (PORT datad (139:139:139) (139:139:139))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_next_0_sqmuxa_7_5_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1143:1143:1143) (1143:1143:1143))
+        (PORT datab (1204:1204:1204) (1204:1204:1204))
+        (PORT datac (359:359:359) (359:359:359))
+        (PORT datad (253:253:253) (253:253:253))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|r_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1451:1451:1451) (1451:1451:1451))
+        (PORT datab (438:438:438) (438:438:438))
+        (PORT datac (1358:1358:1358) (1358:1358:1358))
+        (PORT datad (925:925:925) (925:925:925))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|r_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_control_unit\|b_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1450:1450:1450) (1450:1450:1450))
+        (PORT datab (438:438:438) (438:438:438))
+        (PORT datac (1359:1359:1359) (1359:1359:1359))
+        (PORT datad (927:927:927) (927:927:927))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_control_unit\|b_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (5095:5095:5095) (5095:5095:5095))
+        (PORT clk (2323:2323:2323) (2323:2323:2323))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_hsync_state_3_0_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT datab (954:954:954) (954:954:954))
+        (PORT datac (447:447:447) (447:447:447))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|h_sync_1_0_0_0_g1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (443:443:443) (443:443:443))
+        (PORT datab (435:435:435) (435:435:435))
+        (PORT datac (865:865:865) (865:865:865))
+        (PORT datad (432:432:432) (432:432:432))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1463:1463:1463) (1463:1463:1463))
+        (PORT datab (4923:4923:4923) (4923:4923:4923))
+        (PORT datac (1265:1265:1265) (1265:1265:1265))
+        (PORT datad (352:352:352) (352:352:352))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|h_sync_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2394:2394:2394) (2394:2394:2394))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|un1_vsync_state_2_0_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (620:620:620) (620:620:620))
+        (PORT datad (1246:1246:1246) (1246:1246:1246))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|v_sync_1_0_0_0_g1_cZ\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1374:1374:1374) (1374:1374:1374))
+        (PORT datab (430:430:430) (430:430:430))
+        (PORT datac (378:378:378) (378:378:378))
+        (PORT datad (430:430:430) (430:430:430))
+        (IOPATH dataa combout (459:459:459) (459:459:459))
+        (IOPATH datab combout (332:332:332) (332:332:332))
+        (IOPATH datac combout (213:213:213) (213:213:213))
+        (IOPATH datad combout (87:87:87) (87:87:87))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_lcell")
+    (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lecomb)
+    (DELAY
+      (ABSOLUTE
+        (PORT dataa (1106:1106:1106) (1106:1106:1106))
+        (PORT datab (550:550:550) (550:550:550))
+        (PORT datac (5013:5013:5013) (5013:5013:5013))
+        (PORT datad (2733:2733:2733) (2733:2733:2733))
+        (IOPATH dataa regin (583:583:583) (583:583:583))
+        (IOPATH datab regin (489:489:489) (489:489:489))
+        (IOPATH datac regin (364:364:364) (364:364:364))
+        (IOPATH datad regin (235:235:235) (235:235:235))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_lcell_register")
+    (INSTANCE \\vga_driver_unit\|v_sync_Z\\.lereg)
+    (DELAY
+      (ABSOLUTE
+        (PORT aclr (668:668:668) (668:668:668))
+        (PORT clk (2379:2379:2379) (2379:2379:2379))
+        (IOPATH (posedge clk) regout (176:176:176) (176:176:176))
+        (IOPATH (posedge aclr) regout (212:212:212) (212:212:212))
+      )
+    )
+    (TIMINGCHECK
+      (SETUP datain (posedge clk) (10:10:10))
+      (HOLD datain (posedge clk) (100:100:100))
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE r0_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2578:2578:2578) (2578:2578:2578))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE r1_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2886:2886:2886) (2886:2886:2886))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE r2_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2578:2578:2578) (2578:2578:2578))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE g0_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1963:1963:1963) (1963:1963:1963))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE g1_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2024:2024:2024) (2024:2024:2024))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE g2_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2680:2680:2680) (2680:2680:2680))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE b0_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3590:3590:3590) (3590:3590:3590))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE b1_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3525:3525:3525) (3525:3525:3525))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE hsync_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2183:2183:2183) (2183:2183:2183))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE vsync_pin_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2772:2772:2772) (2772:2772:2772))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2024:2024:2024) (2024:2024:2024))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3263:3263:3263) (3263:3263:3263))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2952:2952:2952) (2952:2952:2952))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1963:1963:1963) (1963:1963:1963))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2024:2024:2024) (2024:2024:2024))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2412:2412:2412) (2412:2412:2412))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1963:1963:1963) (1963:1963:1963))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3263:3263:3263) (3263:3263:3263))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2952:2952:2952) (2952:2952:2952))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_9_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3263:3263:3263) (3263:3263:3263))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_10_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3227:3227:3227) (3227:3227:3227))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_11_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3099:3099:3099) (3099:3099:3099))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_out_12_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3260:3260:3260) (3260:3260:3260))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\seven_seg_pin_tri_13_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2412:2412:2412) (2412:2412:2412))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_hsync_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2183:2183:2183) (2183:2183:2183))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_vsync_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2772:2772:2772) (2772:2772:2772))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2437:2437:2437) (2437:2437:2437))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2426:2426:2426) (2426:2426:2426))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2127:2127:2127) (2127:2127:2127))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2378:2378:2378) (2378:2378:2378))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1826:1826:1826) (1826:1826:1826))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3015:3015:3015) (3015:3015:3015))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2573:2573:2573) (2573:2573:2573))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2118:2118:2118) (2118:2118:2118))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2545:2545:2545) (2545:2545:2545))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_column_counter_out_9_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2104:2104:2104) (2104:2104:2104))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1897:1897:1897) (1897:1897:1897))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1941:1941:1941) (1941:1941:1941))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2564:2564:2564) (2564:2564:2564))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1937:1937:1937) (1937:1937:1937))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2373:2373:2373) (2373:2373:2373))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2612:2612:2612) (2612:2612:2612))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2307:2307:2307) (2307:2307:2307))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2234:2234:2234) (2234:2234:2234))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_line_counter_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2444:2444:2444) (2444:2444:2444))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_set_column_counter_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3234:3234:3234) (3234:3234:3234))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_set_line_counter_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3161:3161:3161) (3161:3161:3161))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2393:2393:2393) (2393:2393:2393))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3712:3712:3712) (3712:3712:3712))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1994:1994:1994) (1994:1994:1994))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2855:2855:2855) (2855:2855:2855))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3074:3074:3074) (3074:3074:3074))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2173:2173:2173) (2173:2173:2173))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3292:3292:3292) (3292:3292:3292))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2319:2319:2319) (2319:2319:2319))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3000:3000:3000) (3000:3000:3000))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_counter_out_9_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3135:3135:3135) (3135:3135:3135))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1986:1986:1986) (1986:1986:1986))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2411:2411:2411) (2411:2411:2411))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2518:2518:2518) (2518:2518:2518))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2074:2074:2074) (2074:2074:2074))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2588:2588:2588) (2588:2588:2588))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2923:2923:2923) (2923:2923:2923))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2434:2434:2434) (2434:2434:2434))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2473:2473:2473) (2473:2473:2473))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2581:2581:2581) (2581:2581:2581))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_counter_out_9_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1951:1951:1951) (1951:1951:1951))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_set_hsync_counter_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2415:2415:2415) (2415:2415:2415))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_set_vsync_counter_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3291:3291:3291) (3291:3291:3291))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_h_enable_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2923:2923:2923) (2923:2923:2923))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_v_enable_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2505:2505:2505) (2505:2505:2505))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_r_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2886:2886:2886) (2886:2886:2886))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_g_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2412:2412:2412) (2412:2412:2412))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_b_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3590:3590:3590) (3590:3590:3590))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2928:2928:2928) (2928:2928:2928))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2651:2651:2651) (2651:2651:2651))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2862:2862:2862) (2862:2862:2862))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2213:2213:2213) (2213:2213:2213))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2164:2164:2164) (2164:2164:2164))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3234:3234:3234) (3234:3234:3234))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_hsync_state_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1944:1944:1944) (1944:1944:1944))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2658:2658:2658) (2658:2658:2658))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2697:2697:2697) (2697:2697:2697))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3588:3588:3588) (3588:3588:3588))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2596:2596:2596) (2596:2596:2596))
+        (IOPATH datain padio (2801:2801:2801) (2801:2801:2801))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3079:3079:3079) (3079:3079:3079))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3161:3161:3161) (3161:3161:3161))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_vsync_state_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2936:2936:2936) (2936:2936:2936))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_state_clk_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2635:2635:2635) (2635:2635:2635))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE d_toggle_out.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2984:2984:2984) (2984:2984:2984))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_0_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1954:1954:1954) (1954:1954:1954))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_1_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2344:2344:2344) (2344:2344:2344))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_2_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2071:2071:2071) (2071:2071:2071))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_3_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3103:3103:3103) (3103:3103:3103))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_4_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2140:2140:2140) (2140:2140:2140))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_5_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2117:2117:2117) (2117:2117:2117))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_6_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2137:2137:2137) (2137:2137:2137))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_7_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2366:2366:2366) (2366:2366:2366))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_8_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2395:2395:2395) (2395:2395:2395))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_9_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2410:2410:2410) (2410:2410:2410))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_10_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2098:2098:2098) (2098:2098:2098))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_11_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (3664:3664:3664) (3664:3664:3664))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_12_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2134:2134:2134) (2134:2134:2134))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_13_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2805:2805:2805) (2805:2805:2805))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_14_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2158:2158:2158) (2158:2158:2158))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_15_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1677:1677:1677) (1677:1677:1677))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_16_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2162:2162:2162) (2162:2162:2162))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_17_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2526:2526:2526) (2526:2526:2526))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_18_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2189:2189:2189) (2189:2189:2189))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_19_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2650:2650:2650) (2650:2650:2650))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_20_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2503:2503:2503) (2503:2503:2503))
+        (IOPATH datain padio (2504:2504:2504) (2504:2504:2504))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_21_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2412:2412:2412) (2412:2412:2412))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_22_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (1963:1963:1963) (1963:1963:1963))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_23_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2680:2680:2680) (2680:2680:2680))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+  (CELL
+    (CELLTYPE "stratix_asynch_io")
+    (INSTANCE \\d_toggle_counter_out_24_\\.inst1)
+    (DELAY
+      (ABSOLUTE
+        (PORT datain (2024:2024:2024) (2024:2024:2024))
+        (IOPATH datain padio (2495:2495:2495) (2495:2495:2495))
+      )
+    )
+  )
+)