--- /dev/null
+{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_PRODUCT" "Classic Timing Analyzer Quartus II " "Info: Running Quartus II Classic Timing Analyzer" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 9.0 Build 132 02/25/2009 SJ Full Version " "Info: Version 9.0 Build 132 02/25/2009 SJ Full Version" { } { } 0 0 "%1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_START_BANNER_TIME" "Wed Oct 28 14:19:50 2009 " "Info: Processing started: Wed Oct 28 14:19:50 2009" { } { } 0 0 "Processing started: %1!s!" 0 0 "" 0 -1} } { } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only " "Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off vga -c vga --timing_analysis_only" { } { } 0 0 "Command: %1!s!" 0 0 "" 0 -1}
+{ "Info" "IQCU_PARALLEL_AUTODETECT_MULTIPLE_PROCESSORS" "2 2 " "Info: Parallel compilation is enabled and will use 2 of the 2 processors detected" { } { } 0 0 "Parallel compilation is enabled and will use %1!i! of the %2!i! processors detected" 0 0 "" 0 -1}
+{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clk_pin " "Info: Assuming node \"clk_pin\" is an undefined clock" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } { "/opt/quartus/quartus/linux/Assignment Editor.qase" "" { Assignment "/opt/quartus/quartus/linux/Assignment Editor.qase" 1 { { 0 "clk_pin" } } } } } 0 0 "Assuming node \"%1!s!\" is an undefined clock" 0 0 "" 0 -1} } { } 0 0 "Found pins functioning as undefined clocks and/or memory enables" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clk_pin register vga_driver:vga_driver_unit\|hsync_counter_8 register vga_driver:vga_driver_unit\|hsync_state_5 191.9 MHz 5.211 ns Internal " "Info: Clock \"clk_pin\" has Internal fmax of 191.9 MHz between source register \"vga_driver:vga_driver_unit\|hsync_counter_8\" and destination register \"vga_driver:vga_driver_unit\|hsync_state_5\" (period= 5.211 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.018 ns + Longest register register " "Info: + Longest register to register delay is 5.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|hsync_counter_8 1 REG LC_X38_Y28_N8 8 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit\|hsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.990 ns) + CELL(0.332 ns) 1.322 ns vga_driver:vga_driver_unit\|un10_hsync_counter_1 2 COMB LC_X41_Y28_N3 4 " "Info: 2: + IC(0.990 ns) + CELL(0.332 ns) = 1.322 ns; Loc. = LC_X41_Y28_N3; Fanout = 4; COMB Node = 'vga_driver:vga_driver_unit\|un10_hsync_counter_1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.322 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 248 28 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.038 ns) + CELL(0.087 ns) 2.447 ns vga_driver:vga_driver_unit\|hsync_state_next_1_sqmuxa_1 3 COMB LC_X36_Y28_N3 1 " "Info: 3: + IC(1.038 ns) + CELL(0.087 ns) = 2.447 ns; Loc. = LC_X36_Y28_N3; Fanout = 1; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_next_1_sqmuxa_1'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.125 ns" { vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 257 35 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.562 ns) + CELL(0.213 ns) 3.222 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 4 COMB LC_X37_Y28_N4 6 " "Info: 4: + IC(0.562 ns) + CELL(0.213 ns) = 3.222 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "0.775 ns" { vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.726 ns) 5.018 ns vga_driver:vga_driver_unit\|hsync_state_5 5 REG LC_X37_Y29_N6 4 " "Info: 5: + IC(1.070 ns) + CELL(0.726 ns) = 5.018 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.796 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.358 ns ( 27.06 % ) " "Info: Total cell delay = 1.358 ns ( 27.06 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "3.660 ns ( 72.94 % ) " "Info: Total interconnect delay = 3.660 ns ( 72.94 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 {} vga_driver:vga_driver_unit|un10_hsync_counter_1 {} vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.990ns 1.038ns 0.562ns 1.070ns } { 0.000ns 0.332ns 0.087ns 0.213ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-0.007 ns - Smallest " "Info: - Smallest clock skew is -0.007 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.255 ns + Shortest register " "Info: + Shortest clock path from clock \"clk_pin\" to destination register is 3.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(0.560 ns) 3.255 ns vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X37_Y29_N6 4 " "Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.387 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.87 % ) " "Info: Total cell delay = 1.428 ns ( 43.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.827 ns ( 56.13 % ) " "Info: Total interconnect delay = 1.827 ns ( 56.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.262 ns - Longest register " "Info: - Longest clock path from clock \"clk_pin\" to source register is 3.262 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.834 ns) + CELL(0.560 ns) 3.262 ns vga_driver:vga_driver_unit\|hsync_counter_8 2 REG LC_X38_Y28_N8 8 " "Info: 2: + IC(1.834 ns) + CELL(0.560 ns) = 3.262 ns; Loc. = LC_X38_Y28_N8; Fanout = 8; REG Node = 'vga_driver:vga_driver_unit\|hsync_counter_8'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.394 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.78 % ) " "Info: Total cell delay = 1.428 ns ( 43.78 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.834 ns ( 56.22 % ) " "Info: Total interconnect delay = 1.834 ns ( 56.22 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%2!c! %3!s! clock skew is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 138 25 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 vga_driver:vga_driver_unit|un10_hsync_counter_1 vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "5.018 ns" { vga_driver:vga_driver_unit|hsync_counter_8 {} vga_driver:vga_driver_unit|un10_hsync_counter_1 {} vga_driver:vga_driver_unit|hsync_state_next_1_sqmuxa_1 {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.990ns 1.038ns 0.562ns 1.070ns } { 0.000ns 0.332ns 0.087ns 0.213ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.262 ns" { clk_pin vga_driver:vga_driver_unit|hsync_counter_8 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.262 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_counter_8 {} } { 0.000ns 0.000ns 1.834ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "Clock \"%1!s!\" has %8!s! fmax of %6!s! between source %2!s! \"%3!s!\" and destination %4!s! \"%5!s!\" (period= %7!s!)" 0 0 "" 0 -1}
+{ "Info" "ITDB_TSU_RESULT" "vga_driver:vga_driver_unit\|hsync_state_5 reset_pin clk_pin 6.543 ns register " "Info: tsu for register \"vga_driver:vga_driver_unit\|hsync_state_5\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is 6.543 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "9.788 ns + Longest pin register " "Info: + Longest pin to register delay is 9.788 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.016 ns) + CELL(0.213 ns) 5.989 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X38_Y30_N2 53 " "Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.229 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.544 ns) + CELL(0.459 ns) 7.992 ns vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0 3 COMB LC_X37_Y28_N4 6 " "Info: 3: + IC(1.544 ns) + CELL(0.459 ns) = 7.992 ns; Loc. = LC_X37_Y28_N4; Fanout = 6; COMB Node = 'vga_driver:vga_driver_unit\|hsync_state_3_0_0_0__g0_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.003 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 246 33 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.070 ns) + CELL(0.726 ns) 9.788 ns vga_driver:vga_driver_unit\|hsync_state_5 4 REG LC_X37_Y29_N6 4 " "Info: 4: + IC(1.070 ns) + CELL(0.726 ns) = 9.788 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.796 ns" { vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.158 ns ( 22.05 % ) " "Info: Total cell delay = 2.158 ns ( 22.05 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "7.630 ns ( 77.95 % ) " "Info: Total interconnect delay = 7.630 ns ( 77.95 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.788 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.788 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 5.016ns 1.544ns 1.070ns } { 0.000ns 0.760ns 0.213ns 0.459ns 0.726ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TSU_DELAY" "0.010 ns + " "Info: + Micro setup delay of destination is 0.010 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%2!c! Micro setup delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.255 ns - Shortest register " "Info: - Shortest clock path from clock \"clk_pin\" to destination register is 3.255 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.827 ns) + CELL(0.560 ns) 3.255 ns vga_driver:vga_driver_unit\|hsync_state_5 2 REG LC_X37_Y29_N6 4 " "Info: 2: + IC(1.827 ns) + CELL(0.560 ns) = 3.255 ns; Loc. = LC_X37_Y29_N6; Fanout = 4; REG Node = 'vga_driver:vga_driver_unit\|hsync_state_5'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.387 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 113 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.87 % ) " "Info: Total cell delay = 1.428 ns ( 43.87 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.827 ns ( 56.13 % ) " "Info: Total interconnect delay = 1.827 ns ( 56.13 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "9.788 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "9.788 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} vga_driver:vga_driver_unit|hsync_state_3_0_0_0__g0_0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 5.016ns 1.544ns 1.070ns } { 0.000ns 0.760ns 0.213ns 0.459ns 0.726ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.255 ns" { clk_pin vga_driver:vga_driver_unit|hsync_state_5 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.255 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|hsync_state_5 {} } { 0.000ns 0.000ns 1.827ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "tsu for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TCO_RESULT" "clk_pin d_set_vsync_counter vga_driver:vga_driver_unit\|vsync_state_0 10.494 ns register " "Info: tco from clock \"clk_pin\" to destination pin \"d_set_vsync_counter\" through register \"vga_driver:vga_driver_unit\|vsync_state_0\" is 10.494 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin source 3.247 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to source register is 3.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(0.560 ns) 3.247 ns vga_driver:vga_driver_unit\|vsync_state_0 2 REG LC_X38_Y30_N9 5 " "Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.379 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.98 % ) " "Info: Total cell delay = 1.428 ns ( 43.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 56.02 % ) " "Info: Total interconnect delay = 1.819 ns ( 56.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TCO_DELAY" "0.176 ns + " "Info: + Micro clock to output delay of source is 0.176 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%2!c! Micro clock to output delay of source is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "7.071 ns + Longest register pin " "Info: + Longest register to pin delay is 7.071 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns vga_driver:vga_driver_unit\|vsync_state_0 1 REG LC_X38_Y30_N9 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X38_Y30_N9; Fanout = 5; REG Node = 'vga_driver:vga_driver_unit\|vsync_state_0'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 109 23 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(0.944 ns) + CELL(0.332 ns) 1.276 ns vga_driver:vga_driver_unit\|d_set_vsync_counter 2 COMB LC_X35_Y30_N4 2 " "Info: 2: + IC(0.944 ns) + CELL(0.332 ns) = 1.276 ns; Loc. = LC_X35_Y30_N4; Fanout = 2; COMB Node = 'vga_driver:vga_driver_unit\|d_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "1.276 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 147 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.291 ns) + CELL(2.504 ns) 7.071 ns d_set_vsync_counter 3 PIN PIN_Y11 0 " "Info: 3: + IC(3.291 ns) + CELL(2.504 ns) = 7.071 ns; Loc. = PIN_Y11; Fanout = 0; PIN Node = 'd_set_vsync_counter'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.795 ns" { vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4454 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.836 ns ( 40.11 % ) " "Info: Total cell delay = 2.836 ns ( 40.11 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "4.235 ns ( 59.89 % ) " "Info: Total interconnect delay = 4.235 ns ( 59.89 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 0.944ns 3.291ns } { 0.000ns 0.332ns 2.504ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin vga_driver:vga_driver_unit|vsync_state_0 } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} vga_driver:vga_driver_unit|vsync_state_0 {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 vga_driver:vga_driver_unit|d_set_vsync_counter d_set_vsync_counter } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "7.071 ns" { vga_driver:vga_driver_unit|vsync_state_0 {} vga_driver:vga_driver_unit|d_set_vsync_counter {} d_set_vsync_counter {} } { 0.000ns 0.944ns 3.291ns } { 0.000ns 0.332ns 2.504ns } "" } } } 0 0 "tco from clock \"%1!s!\" to destination pin \"%2!s!\" through %5!s! \"%3!s!\" is %4!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_FULL_TPD_RESULT" "reset_pin seven_seg_pin\[9\] 11.756 ns Longest " "Info: Longest tpd from source pin \"reset_pin\" to destination pin \"seven_seg_pin\[9\]\" is 11.756 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.016 ns) + CELL(0.213 ns) 5.989 ns vga_driver:vga_driver_unit\|un6_dly_counter_0_x 2 COMB LC_X38_Y30_N2 53 " "Info: 2: + IC(5.016 ns) + CELL(0.213 ns) = 5.989 ns; Loc. = LC_X38_Y30_N2; Fanout = 53; COMB Node = 'vga_driver:vga_driver_unit\|un6_dly_counter_0_x'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.229 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 153 29 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(3.263 ns) + CELL(2.504 ns) 11.756 ns seven_seg_pin\[9\] 3 PIN PIN_A7 0 " "Info: 3: + IC(3.263 ns) + CELL(2.504 ns) = 11.756 ns; Loc. = PIN_A7; Fanout = 0; PIN Node = 'seven_seg_pin\[9\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.767 ns" { vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[9] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4444 30 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.477 ns ( 29.58 % ) " "Info: Total cell delay = 3.477 ns ( 29.58 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "8.279 ns ( 70.42 % ) " "Info: Total interconnect delay = 8.279 ns ( 70.42 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "11.756 ns" { reset_pin vga_driver:vga_driver_unit|un6_dly_counter_0_x seven_seg_pin[9] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "11.756 ns" { reset_pin {} reset_pin~out0 {} vga_driver:vga_driver_unit|un6_dly_counter_0_x {} seven_seg_pin[9] {} } { 0.000ns 0.000ns 5.016ns 3.263ns } { 0.000ns 0.760ns 0.213ns 2.504ns } "" } } } 0 0 "%4!s! tpd from source pin \"%1!s!\" to destination pin \"%2!s!\" is %3!s!" 0 0 "" 0 -1}
+{ "Info" "ITDB_TH_RESULT" "dly_counter\[1\] reset_pin clk_pin -2.787 ns register " "Info: th for register \"dly_counter\[1\]\" (data pin = \"reset_pin\", clock pin = \"clk_pin\") is -2.787 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clk_pin destination 3.247 ns + Longest register " "Info: + Longest clock path from clock \"clk_pin\" to destination register is 3.247 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.868 ns) 0.868 ns clk_pin 1 CLK PIN_R3 84 " "Info: 1: + IC(0.000 ns) + CELL(0.868 ns) = 0.868 ns; Loc. = PIN_R3; Fanout = 84; CLK Node = 'clk_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { clk_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4432 16 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(1.819 ns) + CELL(0.560 ns) 3.247 ns dly_counter\[1\] 2 REG LC_X38_Y30_N6 10 " "Info: 2: + IC(1.819 ns) + CELL(0.560 ns) = 3.247 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "2.379 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.428 ns ( 43.98 % ) " "Info: Total cell delay = 1.428 ns ( 43.98 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "1.819 ns ( 56.02 % ) " "Info: Total interconnect delay = 1.819 ns ( 56.02 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } } 0 0 "%4!c! %5!s! clock path from clock \"%1!s!\" to %2!s! %6!s! is %3!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_TH_DELAY" "0.100 ns + " "Info: + Micro hold delay of destination is 0.100 ns" { } { { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%2!c! Micro hold delay of destination is %1!s!" 0 0 "" 0 -1} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "6.134 ns - Shortest pin register " "Info: - Shortest pin to register delay is 6.134 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.760 ns) 0.760 ns reset_pin 1 PIN PIN_N2 10 " "Info: 1: + IC(0.000 ns) + CELL(0.760 ns) = 0.760 ns; Loc. = PIN_N2; Fanout = 10; PIN Node = 'reset_pin'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "" { reset_pin } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4433 18 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_NODE_DELAY" "IC(5.010 ns) + CELL(0.364 ns) 6.134 ns dly_counter\[1\] 2 REG LC_X38_Y30_N6 10 " "Info: 2: + IC(5.010 ns) + CELL(0.364 ns) = 6.134 ns; Loc. = LC_X38_Y30_N6; Fanout = 10; REG Node = 'dly_counter\[1\]'" { } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "5.374 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "../../syn/rev_1/vga.vqm" "" { Text "/homes/burban/didelu/dide_16/bsp2/Designflow/syn/rev_1/vga.vqm" 4490 24 0 } } } 0 0 "%4!d!: + %1!s! = %2!s!; Loc. = %6!s!; Fanout = %7!d!; %5!s! Node = '%3!s!'" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.124 ns ( 18.32 % ) " "Info: Total cell delay = 1.124 ns ( 18.32 % )" { } { } 0 0 "Total cell delay = %1!s! %2!s!" 0 0 "" 0 -1} { "Info" "ITDB_TOTAL_IC_DELAY" "5.010 ns ( 81.68 % ) " "Info: Total interconnect delay = 5.010 ns ( 81.68 % )" { } { } 0 0 "Total interconnect delay = %1!s! %2!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.134 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.134 ns" { reset_pin {} reset_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 5.010ns } { 0.000ns 0.760ns 0.364ns } "" } } } 0 0 "%2!c! %3!s! %4!s! to %5!s! delay is %1!s!" 0 0 "" 0 -1} } { { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "3.247 ns" { clk_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "3.247 ns" { clk_pin {} clk_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 1.819ns } { 0.000ns 0.868ns 0.560ns } "" } } { "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" { Floorplan "/opt/quartus/quartus/linux/TimingClosureFloorplan.fld" "" "6.134 ns" { reset_pin dly_counter[1] } "NODE_NAME" } } { "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "" { "TechnologyMapViewer" "/opt/quartus/quartus/linux/Technology_Viewer.qrui" "6.134 ns" { reset_pin {} reset_pin~out0 {} dly_counter[1] {} } { 0.000ns 0.000ns 5.010ns } { 0.000ns 0.760ns 0.364ns } "" } } } 0 0 "th for %5!s! \"%1!s!\" (data pin = \"%2!s!\", clock pin = \"%3!s!\") is %4!s!" 0 0 "" 0 -1}
+{ "Info" "IQEXE_ERROR_COUNT" "Classic Timing Analyzer 0 s 1 Quartus II " "Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_PEAK_VSIZE_MEMORY" "141 " "Info: Peak virtual memory: 141 megabytes" { } { } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 -1} { "Info" "IQEXE_END_BANNER_TIME" "Wed Oct 28 14:19:50 2009 " "Info: Processing ended: Wed Oct 28 14:19:50 2009" { } { } 0 0 "Processing ended: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_TIME" "00:00:00 " "Info: Elapsed time: 00:00:00" { } { } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 -1} { "Info" "IQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Info: Total CPU time (on all processors): 00:00:01" { } { } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 -1} } { } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 -1}
projects / dide_16.git / blobdiff