coreboot.git
8 years agoAdd constants for fast path resume copying master
Stefan Reinauer [Tue, 3 Apr 2012 23:21:04 +0000 (16:21 -0700)]
Add constants for fast path resume copying

cache as ram does not usually cache the ram before it is up. Hence,
if romstage.c backs up resume memory, the involved memcpy is always
uncached. This makes resume very slow.
On Sandybridge we copy the memory later, after enabling caching, and
that allows us to resume in as little as 250ms.

Change-Id: I31a71ad4468679d39880cf9a8c4e497bb7addf8f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/872
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoFix timer frequency detection on Sandybridge
Stefan Reinauer [Tue, 3 Apr 2012 23:11:02 +0000 (16:11 -0700)]
Fix timer frequency detection on Sandybridge

Change-Id: Ide720bd91cde56a0afdd231d93500c371b1ffbe8
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/870
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoamdfam10: add phenom II as known cpu
Bernhard Urban [Thu, 5 Apr 2012 15:13:27 +0000 (17:13 +0200)]
amdfam10: add phenom II as known cpu

Change-Id: I84a0f9e8e7a15c0aac8dc380de3ddf70b1decbd7
Signed-off-by: Bernhard Urban <lewurm@gmail.com>
Reviewed-on: http://review.coreboot.org/864
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoInvalidate cache before first jump
Stefan Reinauer [Tue, 3 Apr 2012 23:09:46 +0000 (16:09 -0700)]
Invalidate cache before first jump

Some CPUs (Sandybridge) seem to require this, and it does not hurt
on other CPUs.

Change-Id: I4fdb281b2b684ab5fea999aae28ca08dce24da4d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/869
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agosmbios: Don't fill out firmware version on ChromeOS
Stefan Reinauer [Tue, 3 Apr 2012 23:02:54 +0000 (16:02 -0700)]
smbios: Don't fill out firmware version on ChromeOS

In ChromeOS we potentially have different payloads with
different versions. Since the user land tools get information
on which one of them is loaded, leave the string in smbios
empty so we can fill it out in the payload.
Also fill out system version number and serial number with
some constant values.

Change-Id: Id1fed5a54b511c730975fa83347452f1274b8504
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/867
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoFill out ChromeOS specific coreboot table extensions
Stefan Reinauer [Thu, 5 Apr 2012 19:22:02 +0000 (21:22 +0200)]
Fill out ChromeOS specific coreboot table extensions

ChromeOS uses two extensions to the coreboot table:
- ChromeOS specific GPIO description for onboard switches
- position of verified boot area in nvram

Change-Id: I8c389feec54c00faf2770aafbfd2223ac9da1362
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/866
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoUpdate documentation in smmrelocate.S to mention TSEG
Stefan Reinauer [Wed, 4 Apr 2012 17:38:05 +0000 (10:38 -0700)]
Update documentation in smmrelocate.S to mention TSEG

Change-Id: I392f5fc475b15b458fc015e176e45888e7de27fb
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/861
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd support for Intel Sandybridge CPU
Stefan Reinauer [Tue, 3 Apr 2012 22:09:50 +0000 (00:09 +0200)]
Add support for Intel Sandybridge CPU

Change-Id: I9f37e291c00c0640c6600d8fdd6dcc13c3e5b8d5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/855
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd support for Intel Sandybridge CPU (northbridge part)
Stefan Reinauer [Tue, 3 Apr 2012 22:08:51 +0000 (00:08 +0200)]
Add support for Intel Sandybridge CPU (northbridge part)

Change-Id: I06228ecf9cac931ad34e32871d5a4f2a4857b2ac
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/854
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIgnore .exe files in whitespace test
Patrick Georgi [Thu, 5 Apr 2012 09:18:23 +0000 (11:18 +0200)]
Ignore .exe files in whitespace test

On windows, we sometimes require getopt executables, which end up
in the source tree. These shouldn't break the whitespace test.

Change-Id: Iaf86e38b94605bebb69a317e00f932eefcf468b9
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/863
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd getopt implementation to abuild
Patrick Georgi [Thu, 5 Apr 2012 09:17:01 +0000 (11:17 +0200)]
Add getopt implementation to abuild

Similar to buildgcc, abuild requires getopt(1). Provide an
implementation for platforms without it (Win32)

Change-Id: I2ae4d84e06dd34135c97b18819da2b49a89706ce
Signed-off-by: Patrick Georgi <patrick.georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/862
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoUse fast memset in SMM mode, too
Stefan Reinauer [Fri, 30 Mar 2012 23:28:20 +0000 (16:28 -0700)]
Use fast memset in SMM mode, too

... and always include IP checksumming in romstage.
It's generally useful and our upcoming port needs it.

Change-Id: I248402d96a23e58354744e053b9d5cca6b74ad3a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/827
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd support for Intel Panther Point PCH
Stefan Reinauer [Tue, 3 Apr 2012 22:07:22 +0000 (00:07 +0200)]
Add support for Intel Panther Point PCH

Change-Id: Iac3cd25b36493bb203e849674320e113cc5fce32
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/853
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd support for mainboard specific suspend/resume handler
Stefan Reinauer [Tue, 3 Apr 2012 21:28:22 +0000 (23:28 +0200)]
Add support for mainboard specific suspend/resume handler

Some mainboards (most likely laptops) will need mainboard specific functions
called upon a resume from suspend.

Change-Id: If1518a4b016bba776643adaef0ae64ff49f57e51
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/852
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoMove TPM code to romstage
Stefan Reinauer [Tue, 3 Apr 2012 22:21:37 +0000 (00:21 +0200)]
Move TPM code to romstage

We want to do TPM initialization as early as possible to keep
the impact on boot time low. Therefore move it to romstage.

Change-Id: I5f2e021e0b11bd70a78ad1f05ec09802d015dd9e
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/856
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoDrop verified boot code from acpi.c
Stefan Reinauer [Tue, 3 Apr 2012 16:53:48 +0000 (18:53 +0200)]
Drop verified boot code from acpi.c

We changed our verified boot initialization to run from romstage,
as that allows faster boot times and does not add as much ChromeOS
specific code to generic files.

Change-Id: Id4164c26d524ea0ffce34467cf91379a19a4b2f6
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/851
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoDrop duplicate inclusion of src/vendorcode
Stefan Reinauer [Tue, 3 Apr 2012 22:31:14 +0000 (00:31 +0200)]
Drop duplicate inclusion of src/vendorcode

Change-Id: I95908bdca51c5ee959ae9f2307d4b6e0e002d04a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/857
Reviewed-by: Martin Roth <martin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

8 years agoAdd support to run SMM handler in TSEG instead of ASEG
Stefan Reinauer [Mon, 2 Apr 2012 20:24:04 +0000 (13:24 -0700)]
Add support to run SMM handler in TSEG instead of ASEG

Traditionally coreboot's SMM handler runs in ASEG (0xa0000),
"behind" the graphics memory. This approach has two issues:
- It limits the possible size of the SMM handler (and the
  number of CPUs supported in a system)
- It's not considered a supported path anymore in newer CPUs.

Change-Id: I9f2877e46873ab2ea8f1157ead4bc644a50be19e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Acked-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/842
Reviewed-by: Peter Stuge <peter@stuge.se>
Tested-by: build bot (Jenkins)

8 years agolibpayload: avoid excessive casts in printf.c
Mathias Krause [Tue, 3 Apr 2012 19:02:33 +0000 (21:02 +0200)]
libpayload: avoid excessive casts in printf.c

struct printf_spec is a purely internal structure. Avoid excessive casts
when using the write function pointer just to make the compiler happy by
using the right types in the first place.

Change-Id: Ia4f3c79a5283cb76c8aa5f9d1eee758676303382
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/850
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agolibpayload: minor cleanups
Mathias Krause [Tue, 3 Apr 2012 18:42:01 +0000 (20:42 +0200)]
libpayload: minor cleanups

Apply some const correctness to const/non-const strings in libc and
libpci (what an ugly cast that was).

Remove duplicated NULL test in printf_putstr(), already done in
print_string() - reduces size of libpayload by a few bytes.

Change-Id: I13f479df13e39d79cab291e9d99d153e1ef43eae
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/849
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

8 years agoDon't unconditionally show ChromeOS options
Stefan Reinauer [Tue, 3 Apr 2012 18:22:15 +0000 (11:22 -0700)]
Don't unconditionally show ChromeOS options

Google ChromeOS specific options were shown in the main menu
unconditionally, even on non-ChromeOS devices. Instead, hide
these options unless CONFIG_CHROMEOS is set, and also put them
in a separate menu.

Change-Id: I75f533ed5046d6df4f7d959a0ca4c2441340ef2f
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/848
Reviewed-by: Martin Roth <martin@se-eng.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

8 years agoAdd support for Intel Turbo Boost feature
Stefan Reinauer [Mon, 2 Apr 2012 20:35:09 +0000 (13:35 -0700)]
Add support for Intel Turbo Boost feature

From wikipedia:
Intel Turbo Boost is a technology implemented by Intel in certain
versions of their Nehalem- and Sandy Bridge-based CPUs, including Core
i5 and Core i7 that enables the processor to run above its base
operating frequency via dynamic control of the CPU's "clock rate".
It is activated when the operating system requests the highest
performance state of the processor.

Change-Id: I166ead7c219083006c2b05859eb18749c6fbe832
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/844
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agosmbios: add support for onboard devices extended information
Stefan Reinauer [Mon, 2 Apr 2012 20:30:10 +0000 (13:30 -0700)]
smbios: add support for onboard devices extended information

Add support for type 41 smbios tables (to be used by board
specific smbios handlers)

Change-Id: Id6af5e4b1f5c5c78c63759d24fdc7cf8537ae5e6
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/843
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agonvramtool: 64bit safe CBFS handling
Patrick Georgi [Fri, 9 Mar 2012 11:54:03 +0000 (12:54 +0100)]
nvramtool: 64bit safe CBFS handling

Change-Id: I4f23ee04cd6479e55e9467af1b0196936412deb1
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/846
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd preprocessing capabilities to the cbfs-files mechanism
Patrick Georgi [Fri, 9 Mar 2012 11:30:07 +0000 (12:30 +0100)]
Add preprocessing capabilities to the cbfs-files mechanism

It's now possible to generate files that are about to be added to
CBFS by specifying "sourcefile:method" as real file name.

This makes the build system use the cbfs-files-preprocessor-$(method)
function to create a file from sourcefile. That generated file is
then added to CBFS.

The first method to be defined is "nvramtool". It expects a plain text
specification of the CMOS configuration and emits the binary format
suitable for cmos.default.

Change-Id: I33a142718fc7238eaf5317b0ed62b4726d9b48f2
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/847
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd nvramtool to coreboot build system
Patrick Georgi [Fri, 9 Mar 2012 09:53:52 +0000 (10:53 +0100)]
Add nvramtool to coreboot build system

This way we can depend on it during build.

Change-Id: I7e773c6a029e376e3d70d0a8c9e96ffe0c2cf82e
Signed-off-by: Patrick Georgi <Patrick.Georgi@secunet.com>
Reviewed-on: http://review.coreboot.org/845
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoApply cache-as-ram conditionally on socket mPGA604
Kyösti Mälkki [Tue, 28 Feb 2012 12:01:34 +0000 (14:01 +0200)]
Apply cache-as-ram conditionally on socket mPGA604

The socket mPGA604 is for P4 Xeon which to my knowledge is always
HT-enabled. I assume the existing usage of car/cache_as_ram.inc
on socket_mPGA604, namely the Tyan S2735, as broken.

Existing car/cache_as_ram.inc has invalid SIPI vector and it does
not initialise AP CPU's to activate L2 cache.

Other mPGA604 boards are not affected, as they have not been
converted to CAR.

Change-Id: I7320589695c7f6a695b313a8d0b01b6b1cafbb04
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/607
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoS3 code whitespaces changes.
zbao [Fri, 30 Mar 2012 07:32:07 +0000 (15:32 +0800)]
S3 code whitespaces changes.

some blank changing is integrated into the previous patches, which hold
the unsplitted diff hunk.

Change-Id: If9e5066927c5e27fee7ac8422dbfbf2cbeac7df5
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/625
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

8 years agoAdd sb800 spi support.
zbao [Fri, 23 Mar 2012 03:36:08 +0000 (11:36 +0800)]
Add sb800 spi support.

It is for S3, storing the recovring data in the nonvolatile storage,
i.e., flash.

Change-Id: Ie9e4f42a80c93d92d2e442f0e833ce06d88294f9
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/620
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>

8 years agox86, oprom: ensure DF is always cleared
Mathias Krause [Sun, 1 Apr 2012 09:32:09 +0000 (11:32 +0200)]
x86, oprom: ensure DF is always cleared

The Option ROM might mess with the EFLAGS register and break assumptions
the C part of coreboot implicitly has, e.g. the state of the direction
flag.

Prevent Option ROMs from confusing coreboot by restoring the old EFLAGS
value after the Option ROMs has finished and always clear the direction
flag before calling the C part of the interrupt handler.

Change-Id: I84663be6681b17f95f48d93f0b730e443336b4a8
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/837
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years ago[ChromeOS] Don't initialize VGA Option ROM in normal mode
Stefan Reinauer [Sat, 31 Mar 2012 00:10:49 +0000 (17:10 -0700)]
[ChromeOS] Don't initialize VGA Option ROM in normal mode

ChromeOS features two different modes: normal mode and developer mode
(aka jailbreak mode). In developer mode, we need to display a warning
screen for security reasons.

However, in normal mode we want to boot blazingly fast. Therefore we
don't run (VGA) option ROMs, unless we have to print something on the
screen before the kernel is loaded.

Change-Id: I37f63d0b082a48e037e65bde2b380f9b8743ed29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/829
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd EC component for SMSC MEC1308/1310
Stefan Reinauer [Sat, 31 Mar 2012 00:06:43 +0000 (17:06 -0700)]
Add EC component for SMSC MEC1308/1310

Change-Id: I92109fb633a1a3090b4b1767dd119b8c8a1b5f81
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/828
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd support for ITE IT8772F SuperI/O chip
Stefan Reinauer [Fri, 30 Mar 2012 22:04:07 +0000 (15:04 -0700)]
Add support for ITE IT8772F SuperI/O chip

Change-Id: I8e80c22eb0f3cb68f2457be6b2e7894df60ed632
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/822
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd a helper function to determine the number of enabled CPUs
Stefan Reinauer [Fri, 30 Mar 2012 20:52:58 +0000 (13:52 -0700)]
Add a helper function to determine the number of enabled CPUs

Change-Id: Ia72926002571e0f250849fa5db048bd8b2e92400
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/821
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAlign: Make sure 1 is treated as unsigned long instead of int
Stefan Reinauer [Fri, 30 Mar 2012 20:00:46 +0000 (13:00 -0700)]
Align: Make sure 1 is treated as unsigned long instead of int

... and drop duplicate definition in via/epia-n code.

Change-Id: Id79daaaa35c4d412c8c1f621a3638d129681d331
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/820
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd Google ChromeOS vendor support
Stefan Reinauer [Fri, 30 Mar 2012 19:01:06 +0000 (12:01 -0700)]
Add Google ChromeOS vendor support

Google's ChromeOS can be booted super fast and safely
using coreboot. This adds the ChromeOS specific code that
is required by all ChromeBooks to do this.

Change-Id: Ic03ff090a569a27acbd798ce1e5f89a34897a2f2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/817
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoForce coreboot mconf to create temp files in the output directory
Vadim Bendebury [Mon, 24 Oct 2011 21:06:23 +0000 (14:06 -0700)]
Force coreboot mconf to create temp files in the output directory

This change partially addresses the problem with attempting to
generate coreboot image out of tree. The configuration step fails when
in cheroot, if the destination directory is placed in /tmp.

The problem is that the mconf package tries renaming the temporary
file created in the local directory into the destination config file.
If the destination root and the local directory are located on
different file systems, the rename operation fails.

The proper fix (still upcoming) would be to identify all places where
mconf creates temp files, and make sure that all temp files get
created in the destination tree.

This change modifies just one location, which prevents building out of
tree in the most common case.

Test:
  run the following in the coreboot directory in chroot:
    (coreboot) cp config.lumpy .config
    (coreboot) /bin/rm -rf /tmp/cb
    (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb oldconfig
    (coreboot) CROSS_COMPILE=i686-pc-linux-gnu- make obj=/tmp/cb

  Observe the build succeed (it was failing during the config phase
  before this change)

Change-Id: If4506e984b8afc192a1689c7b0aa956dd35f66c6
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/815
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd a "remove" command to cbfstool
Gabe Black [Fri, 27 Jan 2012 08:33:47 +0000 (00:33 -0800)]
Add a "remove" command to cbfstool

This command removes the first file it finds with the given name by changing
its type to CBFS_COMPONENT_NULL and setting the first character of its name to
a null terminator. If the "files" immediately before or after the target file
are already marked as empty, they're all merged together into one large file.

Change-Id: Idc6b2a4c355c3f039c2ccae81866e3ed6035539b
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-by: Ronald G. Minnich <rminnich@google.com>
Reviewed-on: http://review.coreboot.org/814
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoFix issues with x86 memcpy
Mathias Krause [Sat, 31 Mar 2012 15:23:53 +0000 (17:23 +0200)]
Fix issues with x86 memcpy

The x86 memcpy() implementation did not mention its implicit output
registers ESI, EDI and ECX which might make this code miscompile when
the compiler uses the value of EDI for the return value *after* the 'rep
movsb' has completed. That would break the API of memcpy as this would
return 'dst+len' instead of 'dst'.

Fix this possible bug by removing the wrong comment and listing all
output registers as such (using dummy stack variables that get optimized
away).

Also the leading 'cld' is superflous as the ABI mandates the direction
flag to be cleared all the time when we're in C (see
<http://gcc.gnu.org/gcc-4.3/changes.html>) and we have no ASM call sites
that might require it to be cleared explicitly (SMM might come to mind,
but it clears the DF itself before passing control to the C part of the
SMI handler).

Last but not least fix the prototype to match the one from <string.h>.

Change-Id: I106422d41180c4ed876078cabb26b45e49f3fa93
Signed-off-by: Mathias Krause <minipli@googlemail.com>
Reviewed-on: http://review.coreboot.org/836
Tested-by: build bot (Jenkins)
Reviewed-by: Peter Stuge <peter@stuge.se>

8 years agoWhitespace fixes
Patrick Georgi [Sat, 31 Mar 2012 11:08:12 +0000 (13:08 +0200)]
Whitespace fixes

Change-Id: I441326ecbda72ec7e99fc99bf40a81aa7e94ee26
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/834
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

8 years agoUpdate xcompile to search for x86_64 toolchain.
Marc Jones [Wed, 22 Feb 2012 18:46:17 +0000 (11:46 -0700)]
Update xcompile to search for x86_64 toolchain.

This adds detection of x86_64 gcc toolchain (which buildgcc can build
if provided the option).

Change-Id: I8b12f3e705157741279c7347f4847fb50ccc2b0e
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/673
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>
Tested-by: build bot (Jenkins)

8 years agoMake libpayload parse the coreboot tables before setting up the consoles
Gabe Black [Mon, 5 Mar 2012 23:49:32 +0000 (15:49 -0800)]
Make libpayload parse the coreboot tables before setting up the consoles

At least one of the console drivers, coreboot fb, uses information in the
sysinfo structure to set itself up. If that structure hasn't been populated,
the driver decides that there is no framebuffer and disables itself. Reversing
the order these are set up fixes that problem.

Change-Id: Idd8b5518980dfdd82fd4359dd0133ab7736fc428
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/816
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoEnable -Werror for romcc
Stefan Reinauer [Fri, 30 Mar 2012 19:11:04 +0000 (12:11 -0700)]
Enable -Werror for romcc

... and remove some dead code.

Change-Id: Id959bdf57af09db2a1f5742555c2dcabca38ac9a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/818
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoKeep cscope.out when distclean.
zbao [Fri, 23 Mar 2012 02:26:28 +0000 (10:26 +0800)]
Keep cscope.out when distclean.

It doesnt make sense to delete cscope.out when make
distclean. Distclean is done all the time, and cscope database is also
needed all the time. If we need to delete all the untracked files, we
can use git-clean.

Change-Id: Ic248ccd602ddc88d0b98d5d7f6cbbf530cd82e87
Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Signed-off-by: zbao <fishbaozi@gmail.com>
Reviewed-on: http://review.coreboot.org/831
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoIntel cpus: get MAXPHYADDR at runtime for new CAR
Kyösti Mälkki [Tue, 28 Feb 2012 00:06:45 +0000 (02:06 +0200)]
Intel cpus: get MAXPHYADDR at runtime for new CAR

Use CPUID to get MAXPHYADDR and set MTRR masks correctly.
Also only BSP CPU clears MTRRs and initializes its Local APIC.

Change-Id: I89ee765a17ec7c041284ed402f21d9a969d699bd
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/686
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoIntel cpus: add hyper-threading CPU support to new CAR
Kyösti Mälkki [Tue, 28 Feb 2012 00:02:27 +0000 (02:02 +0200)]
Intel cpus: add hyper-threading CPU support to new CAR

This improvement of CAR code starts the sibling CPU processors and
clears their cache disable bits (CR0.CD) in case a hyper-threading
CPU is detected.

Change-Id: Ieabb86a7c47afb3e178cc75bb89dee3efe0c3d18
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/604
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIntel cpus: improve CPU compatibility of new CAR
Kyösti Mälkki [Thu, 16 Feb 2012 21:12:04 +0000 (23:12 +0200)]
Intel cpus: improve CPU compatibility of new CAR

Most or many Xeons have no MSR 0x11e.

I have previously tested that a HT-enabled P4 (model f25) can
execute this but will not have cache-as-ram enabled. Should work
for non-HT P4.

Change-Id: I28cbfa68858df45a69aa0d5b050cd829d070ad66
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/644
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd support for RAM-less multi-processor init
Kyösti Mälkki [Tue, 14 Feb 2012 08:39:17 +0000 (10:39 +0200)]
Add support for RAM-less multi-processor init

For a hyper-threading processor, enabling cache requires that both the
BSP and AP CPU clear CR0.CD (Cache Disable) bit. For a Cache-As-Ram
implementation, partial multi-processor initialisation precedes
raminit and AP CPUs' 16bit entry must be run from ROM.

The AP CPU can only start execute real-mode code at a 4kB aligned
address below 1MB. The protected mode entry code for AP is identical
with the BSP code, which is already located at the top of bootblock.
This patch takes the simplest approach and aligns the bootblock
16 bit entry at highest possible 4kB boundary below 1MB.

The symbol ap_sipi_vector is tested to match CONFIG_AP_SIPI_VECTOR
used by the CAR code in romstage. Adress is not expected to ever
change, but if it does, link will fail.

Change-Id: I82e4edbf208c9ba863f51a64e50cd92871c528ef
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/454
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIntel cpus: apply some good programming practices in new CAR
Kyösti Mälkki [Mon, 27 Feb 2012 23:45:44 +0000 (01:45 +0200)]
Intel cpus: apply some good programming practices in new CAR

Delete dead CAR code and whitespace fixes.

Replace cryptic 32bit hex values with existing LAPIC definitions.

Do not assume state of direction flag before "rep" instruction.

Do not load immediate values on temporary registers when not needed.

Parameter pushed on stack was not popped (or flushed) after returning
from call. This is a sort-of memory leak if multiple call's are
implemented the same way.

Change-Id: Ibb93e889b3a0af87b89345c462e331881e78686a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/643
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIntel cpus: cache actual size of the Flash ROM device
Kyösti Mälkki [Mon, 27 Feb 2012 22:24:15 +0000 (00:24 +0200)]
Intel cpus: cache actual size of the Flash ROM device

Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.

Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.

Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoIntel cpus: copy model_6ex CAR code
Kyösti Mälkki [Mon, 27 Feb 2012 22:15:30 +0000 (00:15 +0200)]
Intel cpus: copy model_6ex CAR code

Copy model_6ex CAR as car/cache_as_ram_ht.inc to be extended
with hyper-threading CPU support.

Change-Id: I09619363e714b1ebf813932b0b22123c1d89010e
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/606
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoMakefile: rename romstage linking filenames
Kyösti Mälkki [Mon, 26 Mar 2012 16:03:44 +0000 (19:03 +0300)]
Makefile: rename romstage linking filenames

 $(obj)/location.txt ->  $(obj)/romstage/base_xip.txt
 $(obj)/romstage/link1st.ld -> $(obj)/romstage/link_null.ld
 $(obj)/romstage/link2nd.ld -> $(obj)/romstage/link_xip.ld

Change-Id: I15cf29b13a846729f19ecefb21819c4e66681155
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/812
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoMakefile: split romstage linking to separate rules
Kyösti Mälkki [Sat, 31 Mar 2012 07:21:29 +0000 (10:21 +0300)]
Makefile: split romstage linking to separate rules

After change it is more clear how romstage is linked twice and with
what scripts. Also with the change, it is easier to add some
object of static size that need to be re-compiled for the 2nd link.
One such object could be md5sum of executable.

Change-Id: Ib34d1876071a51345c5c7319a0ed937868817fd1
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/803
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoFix coreboot makefiles not to produce half baked output.
Kyösti Mälkki [Sat, 31 Mar 2012 06:48:11 +0000 (09:48 +0300)]
Fix coreboot makefiles not to produce half baked output.

There were cases where output file was generated and modified within
a recipe. If make was interrupted, it could exit with an output file
that appears as up-to-date, but was generated with incomplete recipe.

The output file should be created only when successful, in an atomic
operation. There could be other places in the make system which
require a similar fix, this needs to be investigated further.

Change-Id: I25c8ee23577a460eace196fd28c23cc67aa72a9a
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/830
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoDrop obsolete TINY_BOOTBLOCK
Kyösti Mälkki [Sat, 31 Mar 2012 08:05:52 +0000 (11:05 +0300)]
Drop obsolete TINY_BOOTBLOCK

Change-Id: I0cbb5f7fce91fe65fe8daad00fc43e68337783b0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/832
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

8 years agoFix warnings in coreboot utilities.
Stefan Reinauer [Mon, 14 Nov 2011 20:40:34 +0000 (12:40 -0800)]
Fix warnings in coreboot utilities.

- Fix some poor programming practice (breaks of strict aliasing as well
  as not checking the return value of read)
- Use PRIx64 instead of %llx to prevent compilation warnings with both
  32bit and 64bit compilers
- Use same compiler command options when linking inteltool and when
  detecting libpci for inteltool

Change-Id: I08b2e8d1bbc908f6b1f26d25cb3a4b03d818e124
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/752
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

8 years agouse movsl for copying resume memory back
Stefan Reinauer [Thu, 17 Nov 2011 21:03:38 +0000 (13:03 -0800)]
use movsl for copying resume memory back

It's not significantly faster, but easier to read and smaller.

Change-Id: Ibab0b478873912d67bf1f07743f628586353368a
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/755
Reviewed-by: Mathias Krause <minipli@googlemail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoDon't unconditionally add support for cardbus and pci-x devices
Stefan Reinauer [Wed, 30 Nov 2011 20:45:14 +0000 (12:45 -0800)]
Don't unconditionally add support for cardbus and pci-x devices

It's still on by default.

Change-Id: I8b6539eaf2f8d6a4fa975deb14789a00f2090d34
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/756
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd DEBUG_TPM option to Debugging menu
Stefan Reinauer [Thu, 17 Nov 2011 20:50:54 +0000 (12:50 -0800)]
Add DEBUG_TPM option to Debugging menu

instead of having to edit the source code of tpm.c

Change-Id: I519d9ada14dd383e668a2da4219e5373a24c7c3d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/757
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoMake MTRR min hole alignment 64MB
Duncan Laurie [Tue, 10 Jan 2012 06:05:18 +0000 (22:05 -0800)]
Make MTRR min hole alignment 64MB

This affects the algorithm when determining when to
transform a range into a larger range with a hole.

It is needed when for when I switch on an 8MB TSEG
and cause the memory maps to go crazy.

Also add header defines for the SMRR.

Change-Id: I1a06ccc28ef139cc79f655a8b19fd3533aca0401
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/765
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoFix MB calculation in the reporting of the MTRR hole
Duncan Laurie [Fri, 6 Jan 2012 23:49:30 +0000 (15:49 -0800)]
Fix MB calculation in the reporting of the MTRR hole

Change-Id: I34b5c4ffd2a3f3e895d2bffedce1c00ee9aea942
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/763
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoMTRR: add alternate allocation method for odd memory maps
Duncan Laurie [Thu, 22 Dec 2011 18:59:40 +0000 (10:59 -0800)]
MTRR: add alternate allocation method for odd memory maps

With >= 4GB memory installed we get a memory map split in the middle
due to remap that has boundaries that are inconveniently aligned for
MTRRs due to the various UMA regions.

0000MB-2780MB  2780MB  RAM     (writeback)
2780MB-2782MB     2MB  TSEG    (uncached/SMRR)
2782MB-2784MB     2MB  GFX GTT (uncached)
2784MB-2816MB    32MB  GFX UMA (uncached)
2816MB-4096MB  1280MB  EMPTY   (N/A)
4096MB-5368MB  1272MB  RAM     (writeback)
5368MB-5376MB     8MB  ME UMA  (uncached)

The default MTRR allocation method of trying to cover everything
with one MTRR and then carve out a single uncached region does
not work for the GPU aperture which needs write-combining type,
and it also has issues trying to cover the uneven boundaries
in the avaiable variable MTRRs.

My goal was to make a minimal set of changes and avoid modifying
behavior on existing systems with an algorithm that is not always
optimal for a typical memory layout.  So the flag 'above4gb=2'
will change these allocation behaviors:

1) Detect the number of available variable MTRRs rather than
limiting to hardcoded value.  We need every last MTRR.

2) Don't try to cover all RAM with one MTRR, instead let each
RAM region get covered independently.

3) Don't assume uma_memory_base is part of the last region
and increase the size of that region.  In this case the UMA
region is carved out from the lower memory region and it is
already declared as part of the ram region.

4) If a memory region can't be covered with MTRRs >= 16MB then
instead make a larger region and trim it with uncached MTRRs.

Change-Id: I5a60a44ab6d3ae2f46ea6ffa9e3677aaad2485eb
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/761
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoDon't re-init EBDA in S3 resume path.
Duncan Laurie [Wed, 18 Jan 2012 18:05:18 +0000 (10:05 -0800)]
Don't re-init EBDA in S3 resume path.

I forgot to implement this the first time around.

It does not seem to cause noticeable problems but
in heavy suspend/resume testing I saw a suspicious
crash in the kernel when trying to bring one of the
CPUs back online.

Change-Id: I950ac260f251e2683693d9bd20a0dd5e041aa26e
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/770
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoPrepare the BIOS data areas before device init.
Duncan Laurie [Tue, 17 Jan 2012 17:03:11 +0000 (09:03 -0800)]
Prepare the BIOS data areas before device init.

Since we do not run option roms in normal mode nothing was
initializing the BDA/EBDA and yet Linux depends very much
on it having sane values here.  For the most part the kernel
tries to work around this not being initialized, but every
once in awhile (1/300 boots or so) it would end up reading
something that looked sane from BDA but was not and then
it would panic.

In this change the EBDA is unconditionally setup before devices
are initialized.  I'm not set on the location in dev_initialize()
but there does not seem to be another place to hook it in so
that it runs just once for ALL platforms regardless of whether
they use option roms or not. (possibly hardwaremain?)

The EBDA setup code has been moved into its own location in
arch/x86/lib/ebda.c so it can be compiled in even if the option
rom code is not.

The low memory size is still set to 1MB which is enough to make
linux happy without having to hook into each mainboard to get a
more appropriate value.  The setup_ebda() function takes inputs
so it could be changed for a mainboard if needed.

OLD/BROKEN would read garbage.  Examples from different boots:
ebda_addr=0x75e80 lowmem=0x1553400
ebda_addr=0x5e080 lowmem=0x3e51400
ebda_addr=0x7aa80 lowmem=0x2f8a800

NEW/FIXED now reads consistent values:
ebda_addr=0xf6000 lowmem=0x100000

Change-Id: I6cb79f0e3e43cc65f7e5fe98b6cad1a557ccd949
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/769
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agovga_io.c is not needed unless CONFIG_VGA is set
Stefan Reinauer [Thu, 17 Nov 2011 19:13:36 +0000 (11:13 -0800)]
vga_io.c is not needed unless CONFIG_VGA is set

hence disable it.

Change-Id: I7b406251a2f3830748140a111f76f2792fe923ed
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/753
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAllow components smaller than declared size.
Vadim Bendebury [Wed, 9 Nov 2011 22:11:26 +0000 (14:11 -0800)]
Allow components smaller than declared size.

idftool was failing to add the ME blobs into the output image in case
the blob size does not exactly match the size allocated for it in the
flashrom structure.

It is difficult to set the field in the structure to exactly match the
size (for some reason Intel flash tool fails to insert the correct
size even when given the exact ME blob). On the other hand there is no
harm in using am ME blob smaller than the allocated size, this change
modifies the tool building the image to allow for smaller components.

Change-Id: I1b04f90051b91157391943c9bad0eb06dd297431
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/751
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd Kconfig options to enable TSEG and set a size
Duncan Laurie [Tue, 10 Jan 2012 06:11:25 +0000 (22:11 -0800)]
Add Kconfig options to enable TSEG and set a size

Future CPUs will require TSEG use for SMM

Change-Id: I1432569ece4371d6e12c997e90d66c175fa54c5c
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/766
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoMake cpuid functions usable when compiled with PIC
Duncan Laurie [Tue, 10 Jan 2012 06:00:30 +0000 (22:00 -0800)]
Make cpuid functions usable when compiled with PIC

This avoids using EBX and instead uses EDI where possible,
and ESI when necessary to get the EBX value out.

This allows me to enable -fpic for SMM TSEG code.

Also add a new CPUID extended function to query with ECX set.

Change-Id: I10dbded3f3ad98a39ba7b53da59af6ca3145e2e5
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/764
Tested-by: build bot (Jenkins)
Reviewed-by: Mathias Krause <minipli@googlemail.com>

8 years agoRevamp cbmem.py to use the coreboot tables.
Gabe Black [Sat, 7 Jan 2012 09:03:42 +0000 (01:03 -0800)]
Revamp cbmem.py to use the coreboot tables.

This change makes significant changes to cbmem.py to make it use the
coreboot tables to find the memory console and timestamp areas instead
of looking for the in memory table TOC structure. That appears to be
more robust and gets cbmem.py working again after some unrelated
changes that affected memory layout.

It also introduces some small infrastructure to make accessing C style
structures in physical memory easier and more transparent.

Change-Id: I51833055a50c2d76423520ba6e059bf8fc50adea
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/762
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agodrop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed
Stefan Reinauer [Thu, 15 Dec 2011 17:24:40 +0000 (09:24 -0800)]
drop use of MAX_PHYSICAL_CPUS and MAX_CPUS where not needed

Change-Id: Idf875ddec417e627f1e72a6d834860e7fd324a50
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/760
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoMake PCI CONF2 support a compile time option
Stefan Reinauer [Thu, 17 Nov 2011 21:05:31 +0000 (13:05 -0800)]
Make PCI CONF2 support a compile time option

It's not used on any board supported by coreboot but has been
detected at run time since ages. No new boards (since 2000?)
are using the CONF2 method, so it is unlikely we ever have to
turn this on for a board.

Change-Id: I17df94a8a77b9338fde10a6b114b44d393776e66
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/758
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd more timestamps in coreboot.
Stefan Reinauer [Fri, 4 Nov 2011 19:31:58 +0000 (12:31 -0700)]
Add more timestamps in coreboot.

This adds a number of timestamps in ramstage and romstage
so we can figure out where execution time goes.

Change-Id: Iea17c08774e623fc1ca3fa4505b70523ba4cbf01
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/749
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoFix coreboot makefiles not to produce half baked output.
Vadim Bendebury [Sat, 5 Nov 2011 02:07:01 +0000 (02:07 +0000)]
Fix coreboot makefiles not to produce half baked output.

It looks like the cbfstool utility generates the output file even when
it fails to generate it properly. This causes make, if started second
time in a row, after cbfstool failure, to continue beyond the point of
failure (as the corrupted output file is present in the output tree,
the second make invocation presumes that it is valid, as it is newer
than the dependencies).

The output file should be created only when successful, in an atomic
operation. There could be other places in the make system which
require a similar fix, this needs to be investigated further.

Change-Id: I7c17f033ee5937eb712b1a594122430cee5c9146
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/750
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Tested-by: build bot (Jenkins)

8 years agoAdd timestamps for selfboot and acpi wake
Duncan Laurie [Wed, 19 Oct 2011 22:32:39 +0000 (15:32 -0700)]
Add timestamps for selfboot and acpi wake

Change-Id: I28224867610b947739d940d25c98399d219f10f4
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/733
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoMake TPM driver work in rom stage.
Stefan Reinauer [Thu, 27 Oct 2011 21:28:25 +0000 (21:28 +0000)]
Make TPM driver work in rom stage.

Change-Id: Ifc827d0cd0159aa3f6752d395974f2812334f262
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/738
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoAdd TPM support to coreboot
Stefan Reinauer [Tue, 11 Oct 2011 21:46:25 +0000 (14:46 -0700)]
Add TPM support to coreboot

and initialize the TPM on S3 resume

This patch integrates the TPM driver and runs TPM resume upon an ACPI S3
resume without including any other parts of vboot.

We could link against vboot_fw.a but it is compiled with u-boot's CFLAGS
(that are incompatible with coreboot's) and it does a lot more than we
want it to do.

Change-Id: I000d4322ef313e931e23c56defaa17e3a4d7f8cf
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/731
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd Google ChromeOS vendorcode directory
Stefan Reinauer [Thu, 29 Mar 2012 23:01:51 +0000 (01:01 +0200)]
Add Google ChromeOS vendorcode directory

... and hook it up in Kconfig. More code to come.

Change-Id: I24542d8ef97e2bce112c3aface681ceeb1a7c061
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/813
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd an option to keep the ROM cached after romstage
Stefan Reinauer [Wed, 2 Nov 2011 23:12:34 +0000 (16:12 -0700)]
Add an option to keep the ROM cached after romstage

Change-Id: I05f1cbd33f0cb7d80ec90c636d1607774b4a74ef
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/739
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd native memset() function on x86
Stefan Reinauer [Wed, 26 Oct 2011 22:11:52 +0000 (22:11 +0000)]
Add native memset() function on x86

Change-Id: Ia118ebe0a4b59bdcefd78895141a365170f6aed2
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/737
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoAdd faster, architecture dependent memcpy()
Stefan Reinauer [Tue, 25 Oct 2011 23:43:34 +0000 (23:43 +0000)]
Add faster, architecture dependent memcpy()

Change-Id: I38d15f3f1ec65f0cb7974d2dd4ae6356433bddd8
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/736
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoAdd infrastructure for global data in the CAR phase of boot
Gabe Black [Sat, 1 Oct 2011 11:27:32 +0000 (04:27 -0700)]
Add infrastructure for global data in the CAR phase of boot

The cbmem console structure and car global data are put in their own section,
with the cbmem console coming after the global data. These areas are linked
to be where CAR is available and at the very bottom of the stack.

There is one shortcoming of this change:
The section created by this change needs to be stripped out by the Makefile
since leaving it in confuses cbfstool when it installs the stage in the image.
I would like to make the tools link those symbols at the right location but
leave allocation of that space out of the ELF.

Change-Id: Iccfb99b128d59c5b7d6164796d21ba46d2a674e0
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/727
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoDetect whether the OXPCIE card is really present while in the ROM stage.
Gabe Black [Wed, 5 Oct 2011 08:52:08 +0000 (01:52 -0700)]
Detect whether the OXPCIE card is really present while in the ROM stage.

Use an int in CAR global data to store whether or not the OXPCIE serial card
is actually there. Also, time out if the card doesn't show up quickly enough,
don't continue initialization if it's not there, and don't make the
initialization routine default to a card if none is found.

Change-Id: I9c72d3abc6ee2867b77ab2f2180e6f01f647af8c
Signed-off-by: Gabe Black <gabeblack@google.com>
Reviewed-on: http://review.coreboot.org/728
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoFix typos in src/console/Kconfig
Stefan Reinauer [Tue, 4 Oct 2011 23:21:17 +0000 (16:21 -0700)]
Fix typos in src/console/Kconfig

- cash -> Cache
- make the new size of the cbmem console buffer the default

Change-Id: Ia906077257e93622ad56bc54a42f8184ade78b29
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/726
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoAdd support for enabling PCIe Common Clock and ASPM
Duncan Laurie [Tue, 25 Oct 2011 21:15:11 +0000 (14:15 -0700)]
Add support for enabling PCIe Common Clock and ASPM

These are guarded by individual Kconfig entries. The deprecated
CONFIG_PCIE_TUNING defines have been removed in favor of using specific
config options.

This is the generic half, there is board-specific pieces
still to come that tune before and after ASPM is enabled.

Change-Id: I3fe46282eada67629e9eeeed07e487dff54f2729
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/735
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoRefactor publishing CBMEM addresses through coreboot table.
Vadim Bendebury [Mon, 3 Oct 2011 21:58:57 +0000 (14:58 -0700)]
Refactor publishing CBMEM addresses through coreboot table.

We need to provide u-boot access to several different CBMEM
sections. To do that, a common coreboot table structure is used,
just different tags match different coreboot table sections.

Also, the code is added to export CBMEM console and MRC cache
addresses through the same mechanism.

Change-Id: I63adb67093b8b50ee61b0deb0b56ebb2c4856895
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/724
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd timestamp table pointer to the coreboot table.
Vadim Bendebury [Fri, 23 Sep 2011 16:56:11 +0000 (09:56 -0700)]
Add timestamp table pointer to the coreboot table.

This change exports the timestamp table pointer through coreboot
table to make it possible for u-boot to add timestamps to the
table.

Inclusion of cbmem.h allows to drop external declarations in
coreboot_table.c.

Change-Id: Ia070198cee7a6ffdaeece03d9d15bd91e033b6d1
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/716
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIntroduce utility for parsing CBMEM contents.
Vadim Bendebury [Fri, 30 Sep 2011 21:21:03 +0000 (14:21 -0700)]
Introduce utility for parsing CBMEM contents.

This is a python script which is supposed to run on a target
which is controlled by coreboot. The script examines top of
memory looking for the CBMEM signature at addresses aligned at
128K boundary. Once the script finds the CBMEM, it iterates
through the CBMEM table of contents and parses two entries: the
timestamps and the console log.

This submission is just a template to build upon to create a
utility for displaying CBMEM information while running Linux on
the target.

BUG=chrome-os-partner:4200
TEST=manual

See test description of d81e6b8c8d41f2d6 for test procedure.

Change-Id: Id863a8598eaadc2d20d728f9186843e65cbe6f37
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/5942
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/723
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoCBMEM CONSOLE: Enable coreboot CBMEM console.
Vadim Bendebury [Fri, 30 Sep 2011 19:02:18 +0000 (12:02 -0700)]
CBMEM CONSOLE: Enable coreboot CBMEM console.

The appropriate Makefiles are modified to include the required
source code in compilation.

Change-Id: I91842b1ba0f89d611d3249b63c020a2713a9124f
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/722
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoCBMEM CONSOLE: Add code using the new console driver.
Vadim Bendebury [Fri, 30 Sep 2011 18:16:49 +0000 (11:16 -0700)]
CBMEM CONSOLE: Add code using the new console driver.

The new added code is compiled in when the CBMEM_CONSOLE config
flag is enabled.

Change-Id: Ifd1f492ce6321412a014333babbc5b3f14635988
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/721
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoCBMEM CONSOLE: Add CBMEM type for console buffer.
Vadim Bendebury [Fri, 30 Sep 2011 18:13:06 +0000 (11:13 -0700)]
CBMEM CONSOLE: Add CBMEM type for console buffer.

Add CBMEM type for the console buffer section.

Change-Id: I02757c06d71e46af77b02b90b0e6018a37b62406
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/720
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoCBMEM CONSOLE: Add CBMEM console driver implementation.
Vadim Bendebury [Fri, 30 Sep 2011 00:27:15 +0000 (17:27 -0700)]
CBMEM CONSOLE: Add CBMEM console driver implementation.

The CBMEM console driver saves console output in a CBMEM area, which
then is made available to Linux applications for perusing.

There are some system limitations which need to be worked around
to achieve this goal:

- some console traffic is generated before DRAM is initialized,
  leave alone CBMEM initialized.

- after the RAM based stage starts, a lot of traffic is generated
  before CBMEM is initialized.

As a result, the console log lives in three different places -
the bottom of the cache as RAM space, the CBMEM buffer (where it
is expected to be) and a static buffer used early in the RAM
stage.

When execution starts (in the cache as RAM mode), the console
buffer is allocated at the bottom of the cache as RAM memory
address range. Once DRAM is initialized, the CBMEM structure is
initialized, and then the console buffer contents are copied from
the bottom of the cache as RAM space into the CBMEM area right
before the cache as RAM mode is disabled. The
src/lib/cbmem_console.c:cbmemc_reinit() takes care of the
copying.

At this point the cache as RAM memory is about to be disabled,
but the ROM stage is still going generating console output. To
make sure this output is not lost, cbmemc_reinit() saves the new
buffer address at a fixed location (0x600 was chosen for this),
and the actual "printing" function checks to see if the RAM is
already initialized (the stack is in RAM), and if so, gets the
console buffer pointer from this location instead of using the
cache as RAM address.

When the RAM stage starts, a static buffer is used to store the
console output, as the CBMEM buffer location is not known. Then,
when CBMEM is reinitialized, cbmemc_reinit() again takes care of
the copying.

In case the allocated buffers are not large enough, the excessive
data is dropped, and the copying routine adds some text to the
output buffer to indicate that there has been data lost and how
many characters were dropped.

Change-Id: I8c126e31db6cb2141f7f4f97c5047f39a8db44fc
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/719
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoCBMEM CONSOLE: Add config option for CBMEM stored console log.
Vadim Bendebury [Wed, 28 Sep 2011 20:51:30 +0000 (13:51 -0700)]
CBMEM CONSOLE: Add config option for CBMEM stored console log.

Some experiments have demonstrated that total amount of text
generated by coreboot console when BIOS_SPEW level is enabled
exceeds 40KB.

Console output generated before DRAM is initialized can exceed
2KB. This patch introduces the new configuration option and
assigns adequate default values to cache based and DRAM based
console buffers.

BUG=chrome-os-partner:4200
TEST=manual

 . run the following commands in the root directory

   cp config.stumpy .config
   make menuconfig

 . enable the new option (Console->Send console output to a CBMEM buffer)
 . save the configuration

Observe the following settings added to the config:
+CONFIG_CONSOLE_CBMEM=y
+CONFIG_CONSOLE_CBMEM_BUFFER_SIZE=0xae00
+CONFIG_CONSOLE_CAR_BUFFER_SIZE=0xc00

Change-Id: I209603f516244ae136631e6281ba21ebc6fb1710
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: https://gerrit-int.chromium.org/5855
Tested-by: Vadim Bendebury <vbendeb@google.com>
Reviewed-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/718
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIncrease CBMEM to accommodate larger console.
Vadim Bendebury [Tue, 4 Oct 2011 17:44:16 +0000 (10:44 -0700)]
Increase CBMEM to accommodate larger console.

This change adds 128K to the memory amount set aside for CBMEM in
case the CBMEM console is enabled (to keep the CBMEM 128K byte
aligned). The console buffer size is being set to 64K, which is
enough to accommodate the most verbose coreboot console and
u-boot console.

Change-Id: If583013dfb210de5028d69577675095c6fe2f3ab
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/725
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd cmos helper functions for reading/writing a dword
Duncan Laurie [Mon, 26 Sep 2011 20:24:40 +0000 (13:24 -0700)]
Add cmos helper functions for reading/writing a dword

These get used later for saving/restoring the MRC scrambler
seed values on each boot.

Change-Id: I6e23f17649bea6d22c4b279ed8d0e5cb6c0885e7
Signed-off-by: Duncan Laurie <dlaurie@google.com>
Reviewed-on: http://review.coreboot.org/717
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

8 years agoselfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB
Stefan Reinauer [Tue, 18 Oct 2011 22:11:04 +0000 (15:11 -0700)]
selfboot: Allow loading SeaBIOS into a reserved region in the lower 1MB

This fixes loading SeaBIOS when lower memory is reserved.

Change-Id: Idbdcaf95f3307f97307f304d6d677406d059927d
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/732
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoInclude arch/acpi.h instead of manually adding acpi_slp_type.
Stefan Reinauer [Fri, 23 Sep 2011 17:24:49 +0000 (10:24 -0700)]
Include arch/acpi.h instead of manually adding acpi_slp_type.

acpi_slp_type is defined in arch/acpi.h, so let's use that instead
of manually spreading extern u8 acpi_slp_type throughout the code.

Change-Id: Ia5eb420364c15ab5a764bc328bbd201ca9cb7837
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Reviewed-on: http://review.coreboot.org/714
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoAdd timestamp collecting to coreboot.
Vadim Bendebury [Wed, 21 Sep 2011 23:12:39 +0000 (16:12 -0700)]
Add timestamp collecting to coreboot.

This patch adds code to initialize the time stamp collection
facility in coreboot. It adds a table in the CBMEM section, which
provides the base timer reading value (all other readings are
offsets of this one) and an array of timestamp id/timestamp value
pairs.

Just two values are being added now, this will have to be used
more extensively and also integrated into payloads to provide more
comprehensive boot process time measurements.

Also, since the CBMEM area could already contain a section (from the
previous run, before reset), when processing a section addition
request we should check if a section already exists and return its
address, if so.

Change-Id: I7ed9f5c400bc5432f228348b41fd19a67c36d533
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/713
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)

8 years agoAdd a config flag to enable time stamp collection
Vadim Bendebury [Wed, 21 Sep 2011 21:46:43 +0000 (14:46 -0700)]
Add a config flag to enable time stamp collection

Add a new flag, make it dependent on EARLY_CBMEM_INIT

Change-Id: Idbebcaf298238f31a73e9eb4a9af7b03e857bc74
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/712
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Rudolf Marek <r.marek@assembler.cz>

8 years agoInitialize CBMEM early.
Vadim Bendebury [Wed, 21 Sep 2011 00:07:14 +0000 (17:07 -0700)]
Initialize CBMEM early.

We want to be able to share data between different phases of firmware
(rom stage/ram stage/payload). Coreboot CBMEM seems an appropriate
location for this data, but normally it is not initialized
until coreboot reaches the ram stage.

This change initializes the CBMEM while still in rom stage in
case CONFIG_EARLY_CBMEM_INIT is set.

Note that there is a discrepancy in how coreboot determines the
size of DRAM at rom and ram stages, get_top_of_ram() is used at
rom stage and is not defined for all platforms. Those platforms
will have to define this function should they enable the
CONFIG_EARLY_CBMEM_INIT flag.

Change-Id: I81691d45e28de59496fb227f2cca4e8c15ece717
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/711
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

8 years agoIntroduce config option to initialize CBMEM early.
Vadim Bendebury [Tue, 20 Sep 2011 23:46:46 +0000 (16:46 -0700)]
Introduce config option to initialize CBMEM early.

We want to be able to communicate information between rom and ram
stages of coreboot. This configuration option will be used to
compile such ability in.

Change-Id: I6736fdc264ecd0b63369b28462d7bb96e4c2b012
Signed-off-by: Vadim Bendebury <vbendeb@chromium.org>
Reviewed-on: http://review.coreboot.org/710
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>