Add support for Intel Panther Point PCH

[coreboot.git] / src / southbridge / intel / bd82x6x / gpio.c

diff --git a/src/southbridge/intel/bd82x6x/gpio.c b/src/southbridge/intel/bd82x6x/gpio.c
new file mode 100644 (file)
index 0000000..598726a
--- /dev/null
+++ b/src/southbridge/intel/bd82x6x/gpio.c
@@ -0,0 +1,65 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <stdint.h>
+#include <string.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+
+#include "pch.h"
+#include "gpio.h"
+
+void setup_pch_gpios(const struct pch_gpio_map *gpio)
+{
+       u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
+
+       /* GPIO Set 1 */
+       if (gpio->set1.level)
+               outl(*((u32*)gpio->set1.level), gpiobase + GP_LVL);
+       if (gpio->set1.mode)
+               outl(*((u32*)gpio->set1.mode), gpiobase + GPIO_USE_SEL);
+       if (gpio->set1.direction)
+               outl(*((u32*)gpio->set1.direction), gpiobase + GP_IO_SEL);
+       if (gpio->set1.reset)
+               outl(*((u32*)gpio->set1.reset), gpiobase + GP_RST_SEL1);
+       if (gpio->set1.invert)
+               outl(*((u32*)gpio->set1.invert), gpiobase + GPI_INV);
+       if (gpio->set1.blink)
+               outl(*((u32*)gpio->set1.blink), gpiobase + GPO_BLINK);
+
+       /* GPIO Set 2 */
+       if (gpio->set2.level)
+               outl(*((u32*)gpio->set2.level), gpiobase + GP_LVL2);
+       if (gpio->set2.mode)
+               outl(*((u32*)gpio->set2.mode), gpiobase + GPIO_USE_SEL2);
+       if (gpio->set2.direction)
+               outl(*((u32*)gpio->set2.direction), gpiobase + GP_IO_SEL2);
+       if (gpio->set2.reset)
+               outl(*((u32*)gpio->set2.reset), gpiobase + GP_RST_SEL2);
+
+       /* GPIO Set 3 */
+       if (gpio->set3.level)
+               outl(*((u32*)gpio->set3.level), gpiobase + GP_LVL3);
+       if (gpio->set3.mode)
+               outl(*((u32*)gpio->set3.mode), gpiobase + GPIO_USE_SEL3);
+       if (gpio->set3.direction)
+               outl(*((u32*)gpio->set3.direction), gpiobase + GP_IO_SEL3);
+       if (gpio->set3.reset)
+               outl(*((u32*)gpio->set3.reset), gpiobase + GP_RST_SEL3);
+}