Add support for Intel Sandybridge CPU (northbridge part)

[coreboot.git] / src / northbridge / intel / sandybridge / acpi.c

diff --git a/src/northbridge/intel/sandybridge/acpi.c b/src/northbridge/intel/sandybridge/acpi.c
new file mode 100644 (file)
index 0000000..d1174d6
--- /dev/null
+++ b/src/northbridge/intel/sandybridge/acpi.c
@@ -0,0 +1,75 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <types.h>
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <arch/acpigen.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "sandybridge.h"
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+       device_t dev;
+       u32 pciexbar = 0;
+       u32 pciexbar_reg;
+       int max_buses;
+
+       dev = dev_find_device(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_NB, 0);
+       if (!dev)
+               return current;
+
+       pciexbar_reg=pci_read_config32(dev, PCIEXBAR);
+
+       // MMCFG not supported or not enabled.
+       if (!(pciexbar_reg & (1 << 0)))
+               return current;
+
+       switch ((pciexbar_reg >> 1) & 3) {
+       case 0: // 256MB
+               pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
+               max_buses = 256;
+               break;
+       case 1: // 128M
+               pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
+               max_buses = 128;
+               break;
+       case 2: // 64M
+               pciexbar = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
+               max_buses = 64;
+               break;
+       default: // RSVD
+               return current;
+       }
+
+       if (!pciexbar)
+               return current;
+
+       current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+                       pciexbar, 0x0, 0x0, max_buses - 1);
+
+       return current;
+}
+
+