+++ /dev/null
-TimeQuest Timing Analyzer report for dt
-Mon Dec 20 17:38:57 2010
-Quartus II Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
-
-
----------------------
-; Table of Contents ;
----------------------
- 1. Legal Notice
- 2. TimeQuest Timing Analyzer Summary
- 3. Parallel Compilation
- 4. Clocks
- 5. Fmax Summary
- 6. Setup Summary
- 7. Hold Summary
- 8. Recovery Summary
- 9. Removal Summary
- 10. Minimum Pulse Width Summary
- 11. Setup: 'sys_clk'
- 12. Hold: 'sys_clk'
- 13. Minimum Pulse Width: 'sys_clk'
- 14. Setup Times
- 15. Hold Times
- 16. Clock to Output Times
- 17. Minimum Clock to Output Times
- 18. Setup Transfers
- 19. Hold Transfers
- 20. Report TCCS
- 21. Report RSKM
- 22. Unconstrained Paths
- 23. TimeQuest Timing Analyzer Messages
-
-
-
-----------------
-; Legal Notice ;
-----------------
-Copyright (C) 1991-2010 Altera Corporation
-Your use of Altera Corporation's design tools, logic functions
-and other software and tools, and its AMPP partner logic
-functions, and any output files from any of the foregoing
-(including device programming or simulation files), and any
-associated documentation or information are expressly subject
-to the terms and conditions of the Altera Program License
-Subscription Agreement, Altera MegaCore Function License
-Agreement, or other applicable license agreement, including,
-without limitation, that your use is for the sole purpose of
-programming logic devices manufactured by Altera and sold by
-Altera or its authorized distributors. Please refer to the
-applicable agreement for further details.
-
-
-
-+--------------------------------------------------------------------------------------+
-; TimeQuest Timing Analyzer Summary ;
-+--------------------+-----------------------------------------------------------------+
-; Quartus II Version ; Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition ;
-; Revision Name ; dt ;
-; Device Family ; Cyclone ;
-; Device Name ; EP1C12Q240C8 ;
-; Timing Models ; Final ;
-; Delay Model ; Slow Model ;
-; Rise/Fall Delays ; Unavailable ;
-+--------------------+-----------------------------------------------------------------+
-
-
-Parallel compilation was disabled, but you have multiple processors available. Enable parallel compilation to reduce compilation time.
-+-------------------------------------+
-; Parallel Compilation ;
-+----------------------------+--------+
-; Processors ; Number ;
-+----------------------------+--------+
-; Number detected on machine ; 2 ;
-; Maximum allowed ; 1 ;
-+----------------------------+--------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Clocks ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
-; Clock Name ; Type ; Period ; Frequency ; Rise ; Fall ; Duty Cycle ; Divide by ; Multiply by ; Phase ; Offset ; Edge List ; Edge Shift ; Inverted ; Master ; Source ; Targets ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
-; sys_clk ; Base ; 1.000 ; 1000.0 MHz ; 0.000 ; 0.500 ; ; ; ; ; ; ; ; ; ; ; { sys_clk } ;
-+------------+------+--------+------------+-------+-------+------------+-----------+-------------+-------+--------+-----------+------------+----------+--------+--------+-------------+
-
-
-+-------------------------------------------------+
-; Fmax Summary ;
-+-----------+-----------------+------------+------+
-; Fmax ; Restricted Fmax ; Clock Name ; Note ;
-+-----------+-----------------+------------+------+
-; 47.07 MHz ; 47.07 MHz ; sys_clk ; ;
-+-----------+-----------------+------------+------+
-This panel reports FMAX for every clock in the design, regardless of the user-specified clock periods. FMAX is only computed for paths where the source and destination registers or ports are driven by the same clock. Paths of different clocks, including generated clocks, are ignored. For paths between a clock and its inversion, FMAX is computed as if the rising and falling edges are scaled along with FMAX, such that the duty cycle (in terms of a percentage) is maintained. Altera recommends that you always use clock constraints and other slack reports for sign-off analysis.
-
-
-+-----------------------------------+
-; Setup Summary ;
-+---------+---------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+---------+---------+---------------+
-; sys_clk ; -20.245 ; -16040.760 ;
-+---------+---------+---------------+
-
-
-+---------------------------------+
-; Hold Summary ;
-+---------+-------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+---------+-------+---------------+
-; sys_clk ; 0.822 ; 0.000 ;
-+---------+-------+---------------+
-
-
---------------------
-; Recovery Summary ;
---------------------
-No paths to report.
-
-
--------------------
-; Removal Summary ;
--------------------
-No paths to report.
-
-
-+----------------------------------+
-; Minimum Pulse Width Summary ;
-+---------+--------+---------------+
-; Clock ; Slack ; End Point TNS ;
-+---------+--------+---------------+
-; sys_clk ; -2.003 ; -4074.623 ;
-+---------+--------+---------------+
-
-
-+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Setup: 'sys_clk' ;
-+---------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+---------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.245 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a28~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 21.142 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.150 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a20~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.106 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.138 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a18~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.094 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.096 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a21~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.007 ; 21.052 ;
-; -20.047 ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.142 ; 20.868 ;
-; -20.047 ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.142 ; 20.868 ;
-; -20.047 ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.142 ; 20.868 ;
-; -20.047 ; decode_stage:decode_st|r2_w_ram:register_ram|altsyncram:ram_rtl_2|altsyncram_emk1:auto_generated|ram_block1a2~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.142 ; 20.868 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -20.032 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a24~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.107 ; 20.888 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.972 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a25~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.869 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.934 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a16~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.074 ; 20.823 ;
-; -19.897 ; writeback_stage:writeback_st|wb_reg.address[24] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.059 ; 20.801 ;
-; -19.896 ; writeback_stage:writeback_st|wb_reg.address[8] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.059 ; 20.800 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg6 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg7 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg8 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg9 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.888 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a17~portb_address_reg10 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.785 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg0 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg1 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg2 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg3 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg4 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-; -19.857 ; writeback_stage:writeback_st|r_w_ram:data_ram|altsyncram:ram_rtl_3|altsyncram_grk1:auto_generated|ram_block1a29~portb_address_reg5 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.zero ; sys_clk ; sys_clk ; 1.000 ; -0.066 ; 20.754 ;
-+---------+-------------------------------------------------------------------------------------------------------------------------------------+---------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
-; Hold: 'sys_clk' ;
-+-------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; Slack ; From Node ; To Node ; Launch Clock ; Latch Clock ; Relationship ; Clock Skew ; Data Delay ;
-+-------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-; 0.822 ; execute_stage:exec_st|reg.alu_jump ; execute_stage:exec_st|reg.alu_jump ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 0.837 ;
-; 0.864 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_res_int[5] ; writeback_stage:writeback_st|extension_uart:uart|w4_uart_receive[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 0.879 ;
-; 1.031 ; writeback_stage:writeback_st|wb_reg.data[20] ; writeback_stage:writeback_st|extension_uart:uart|w1_st_co[20] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.046 ;
-; 1.032 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.047 ;
-; 1.032 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.047 ;
-; 1.039 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.054 ;
-; 1.039 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.054 ;
-; 1.050 ; writeback_stage:writeback_st|wb_reg.data[11] ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[11] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.065 ;
-; 1.057 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_STOP ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.072 ;
-; 1.074 ; execute_stage:exec_st|reg.brpr ; execute_stage:exec_st|reg.brpr ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.089 ;
-; 1.074 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[31] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.089 ;
-; 1.142 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.157 ;
-; 1.224 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.239 ;
-; 1.225 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.240 ;
-; 1.234 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.status.oflo ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.249 ;
-; 1.238 ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; execute_stage:exec_st|extension_gpm:gpmp_inst|reg.preg[0][0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.253 ;
-; 1.239 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_BIT ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.254 ;
-; 1.248 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.263 ;
-; 1.250 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.265 ;
-; 1.256 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|state.READ_START ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.271 ;
-; 1.271 ; writeback_stage:writeback_st|wb_reg.address[3] ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.286 ;
-; 1.277 ; writeback_stage:writeback_st|wb_reg.data[3] ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.292 ;
-; 1.285 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|idle_sig ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.300 ;
-; 1.290 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.305 ;
-; 1.291 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.306 ;
-; 1.292 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.307 ;
-; 1.293 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.308 ;
-; 1.294 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.309 ;
-; 1.295 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.310 ;
-; 1.296 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.311 ;
-; 1.297 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.312 ;
-; 1.298 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.313 ;
-; 1.299 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.314 ;
-; 1.299 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[2] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit0[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.314 ;
-; 1.299 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.314 ;
-; 1.300 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.315 ;
-; 1.301 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[15] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit3[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.316 ;
-; 1.312 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.327 ;
-; 1.312 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|baud_cnt[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.327 ;
-; 1.326 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.341 ;
-; 1.326 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[11] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.341 ;
-; 1.326 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[16] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.341 ;
-; 1.326 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[21] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.341 ;
-; 1.327 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[20] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.342 ;
-; 1.328 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[10] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.343 ;
-; 1.328 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[14] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.343 ;
-; 1.328 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[24] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.343 ;
-; 1.329 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[9] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.344 ;
-; 1.329 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[19] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.344 ;
-; 1.338 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.353 ;
-; 1.339 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[26] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.354 ;
-; 1.339 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.354 ;
-; 1.339 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.354 ;
-; 1.340 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.355 ;
-; 1.341 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.356 ;
-; 1.344 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[30] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.359 ;
-; 1.344 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.359 ;
-; 1.346 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.361 ;
-; 1.346 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.361 ;
-; 1.348 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.363 ;
-; 1.348 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.363 ;
-; 1.349 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.364 ;
-; 1.349 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.364 ;
-; 1.350 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[7] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.365 ;
-; 1.351 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.366 ;
-; 1.351 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[10] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.366 ;
-; 1.355 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[29] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.370 ;
-; 1.356 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.371 ;
-; 1.359 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.374 ;
-; 1.360 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[1] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.375 ;
-; 1.362 ; execute_stage:exec_st|reg.brpr ; fetch_stage:fetch_st|instr_r_addr[10] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.377 ;
-; 1.392 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.407 ;
-; 1.393 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.408 ;
-; 1.395 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.410 ;
-; 1.397 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.412 ;
-; 1.398 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.413 ;
-; 1.400 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.415 ;
-; 1.401 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[4] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.416 ;
-; 1.403 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.418 ;
-; 1.403 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[6] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.418 ;
-; 1.404 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.419 ;
-; 1.405 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.420 ;
-; 1.406 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[5] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit1[1] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.421 ;
-; 1.406 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.421 ;
-; 1.407 ; writeback_stage:writeback_st|extension_7seg:sseg|ext_reg_r.data[9] ; writeback_stage:writeback_st|extension_7seg:sseg|s_state.digit2[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.422 ;
-; 1.419 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.434 ;
-; 1.423 ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[2] ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|cnt[3] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.438 ;
-; 1.470 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[0] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.485 ;
-; 1.473 ; writeback_stage:writeback_st|extension_uart:uart|new_tx_data ; writeback_stage:writeback_st|extension_uart:uart|rs232_tx:rs232_tx_inst|state ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.488 ;
-; 1.474 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[2] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.489 ;
-; 1.476 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[7] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.491 ;
-; 1.476 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[12] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.491 ;
-; 1.476 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[17] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.491 ;
-; 1.476 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[22] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.491 ;
-; 1.476 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|rx_data_int[5] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.491 ;
-; 1.480 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[8] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.495 ;
-; 1.480 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[18] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.495 ;
-; 1.481 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[13] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.496 ;
-; 1.481 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[23] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.496 ;
-; 1.482 ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; writeback_stage:writeback_st|extension_uart:uart|rs232_rx:rs232_rx_inst|cnt[15] ; sys_clk ; sys_clk ; 0.000 ; 0.000 ; 1.497 ;
-+-------+--------------------------------------------------------------------------------------------+------------------------------------------------------------------------------------------+--------------+-------------+--------------+------------+------------+
-
-
-+----------------------------------------------------------------------------------------------------------------------------------------------+
-; Minimum Pulse Width: 'sys_clk' ;
-+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------------+
-; Slack ; Actual Width ; Required Width ; Type ; Clock ; Clock Edge ; Target ;
-+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------------+
-; -2.003 ; 1.000 ; 3.003 ; Port Rate ; sys_clk ; Rise ; sys_clk ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.brpr ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.brpr ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[0] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[0] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[1] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[1] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[2] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[2] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[3] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.condition[3] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[0] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[0] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[1] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[1] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[2] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[2] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[3] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.daddr[3] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[0] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[10] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[11] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[12] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[13] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[1] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[1] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[2] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[31] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[31] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[3] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[3] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[4] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[4] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[5] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[6] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[7] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[7] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[8] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.displacement[9] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[1] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[1] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[2] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[2] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM067 ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM067 ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[3]_RTM072 ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[4] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[4] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[5] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_detail[5] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.ADDSUB_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.AND_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM069 ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM069 ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM070 ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM070 ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM071 ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_OP_RTM071 ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.JMP_ST_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.LDST_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.OR_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.SHIFT_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.STACK_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.op_group.XOR_OP ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[0] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[0] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[10] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[10] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[1] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[1] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[2] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[2] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[3] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[3] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[4] ;
-; -1.318 ; 0.500 ; 1.818 ; Low Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[4] ;
-; -1.318 ; 0.500 ; 1.818 ; High Pulse Width ; sys_clk ; Rise ; decode_stage:decode_st|dec_op_inst.prog_cnt[5] ;
-+--------+--------------+----------------+------------------+---------+------------+-----------------------------------------------------------+
-
-
-+-------------------------------------------------------------------------+
-; Setup Times ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; bus_rx ; sys_clk ; 4.012 ; 4.012 ; Rise ; sys_clk ;
-; sys_res ; sys_clk ; 19.693 ; 19.693 ; Rise ; sys_clk ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-------------------------------------------------------------------------+
-; Hold Times ;
-+-----------+------------+--------+--------+------------+-----------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+--------+--------+------------+-----------------+
-; bus_rx ; sys_clk ; -3.960 ; -3.960 ; Rise ; sys_clk ;
-; sys_res ; sys_clk ; -5.597 ; -5.597 ; Rise ; sys_clk ;
-+-----------+------------+--------+--------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Clock to Output Times ;
-+-----------+------------+-------+-------+------------+-----------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+-------+-------+------------+-----------------+
-; bus_tx ; sys_clk ; 7.760 ; 7.760 ; Rise ; sys_clk ;
-; sseg0[*] ; sys_clk ; 8.450 ; 8.450 ; Rise ; sys_clk ;
-; sseg0[0] ; sys_clk ; 8.448 ; 8.448 ; Rise ; sys_clk ;
-; sseg0[1] ; sys_clk ; 8.210 ; 8.210 ; Rise ; sys_clk ;
-; sseg0[2] ; sys_clk ; 7.782 ; 7.782 ; Rise ; sys_clk ;
-; sseg0[3] ; sys_clk ; 7.783 ; 7.783 ; Rise ; sys_clk ;
-; sseg0[4] ; sys_clk ; 8.096 ; 8.096 ; Rise ; sys_clk ;
-; sseg0[5] ; sys_clk ; 8.450 ; 8.450 ; Rise ; sys_clk ;
-; sseg0[6] ; sys_clk ; 8.201 ; 8.201 ; Rise ; sys_clk ;
-; sseg1[*] ; sys_clk ; 8.471 ; 8.471 ; Rise ; sys_clk ;
-; sseg1[0] ; sys_clk ; 8.053 ; 8.053 ; Rise ; sys_clk ;
-; sseg1[1] ; sys_clk ; 8.227 ; 8.227 ; Rise ; sys_clk ;
-; sseg1[2] ; sys_clk ; 8.127 ; 8.127 ; Rise ; sys_clk ;
-; sseg1[3] ; sys_clk ; 8.078 ; 8.078 ; Rise ; sys_clk ;
-; sseg1[4] ; sys_clk ; 7.809 ; 7.809 ; Rise ; sys_clk ;
-; sseg1[5] ; sys_clk ; 8.471 ; 8.471 ; Rise ; sys_clk ;
-; sseg1[6] ; sys_clk ; 8.043 ; 8.043 ; Rise ; sys_clk ;
-; sseg2[*] ; sys_clk ; 8.554 ; 8.554 ; Rise ; sys_clk ;
-; sseg2[0] ; sys_clk ; 8.155 ; 8.155 ; Rise ; sys_clk ;
-; sseg2[1] ; sys_clk ; 7.784 ; 7.784 ; Rise ; sys_clk ;
-; sseg2[2] ; sys_clk ; 7.778 ; 7.778 ; Rise ; sys_clk ;
-; sseg2[3] ; sys_clk ; 8.554 ; 8.554 ; Rise ; sys_clk ;
-; sseg2[4] ; sys_clk ; 8.452 ; 8.452 ; Rise ; sys_clk ;
-; sseg2[5] ; sys_clk ; 7.780 ; 7.780 ; Rise ; sys_clk ;
-; sseg2[6] ; sys_clk ; 8.264 ; 8.264 ; Rise ; sys_clk ;
-; sseg3[*] ; sys_clk ; 7.876 ; 7.876 ; Rise ; sys_clk ;
-; sseg3[0] ; sys_clk ; 7.689 ; 7.689 ; Rise ; sys_clk ;
-; sseg3[1] ; sys_clk ; 7.275 ; 7.275 ; Rise ; sys_clk ;
-; sseg3[2] ; sys_clk ; 7.274 ; 7.274 ; Rise ; sys_clk ;
-; sseg3[3] ; sys_clk ; 7.276 ; 7.276 ; Rise ; sys_clk ;
-; sseg3[4] ; sys_clk ; 7.720 ; 7.720 ; Rise ; sys_clk ;
-; sseg3[5] ; sys_clk ; 7.272 ; 7.272 ; Rise ; sys_clk ;
-; sseg3[6] ; sys_clk ; 7.876 ; 7.876 ; Rise ; sys_clk ;
-+-----------+------------+-------+-------+------------+-----------------+
-
-
-+-----------------------------------------------------------------------+
-; Minimum Clock to Output Times ;
-+-----------+------------+-------+-------+------------+-----------------+
-; Data Port ; Clock Port ; Rise ; Fall ; Clock Edge ; Clock Reference ;
-+-----------+------------+-------+-------+------------+-----------------+
-; bus_tx ; sys_clk ; 7.760 ; 7.760 ; Rise ; sys_clk ;
-; sseg0[*] ; sys_clk ; 7.782 ; 7.782 ; Rise ; sys_clk ;
-; sseg0[0] ; sys_clk ; 8.448 ; 8.448 ; Rise ; sys_clk ;
-; sseg0[1] ; sys_clk ; 8.210 ; 8.210 ; Rise ; sys_clk ;
-; sseg0[2] ; sys_clk ; 7.782 ; 7.782 ; Rise ; sys_clk ;
-; sseg0[3] ; sys_clk ; 7.783 ; 7.783 ; Rise ; sys_clk ;
-; sseg0[4] ; sys_clk ; 8.096 ; 8.096 ; Rise ; sys_clk ;
-; sseg0[5] ; sys_clk ; 8.450 ; 8.450 ; Rise ; sys_clk ;
-; sseg0[6] ; sys_clk ; 8.201 ; 8.201 ; Rise ; sys_clk ;
-; sseg1[*] ; sys_clk ; 7.809 ; 7.809 ; Rise ; sys_clk ;
-; sseg1[0] ; sys_clk ; 8.053 ; 8.053 ; Rise ; sys_clk ;
-; sseg1[1] ; sys_clk ; 8.227 ; 8.227 ; Rise ; sys_clk ;
-; sseg1[2] ; sys_clk ; 8.127 ; 8.127 ; Rise ; sys_clk ;
-; sseg1[3] ; sys_clk ; 8.078 ; 8.078 ; Rise ; sys_clk ;
-; sseg1[4] ; sys_clk ; 7.809 ; 7.809 ; Rise ; sys_clk ;
-; sseg1[5] ; sys_clk ; 8.471 ; 8.471 ; Rise ; sys_clk ;
-; sseg1[6] ; sys_clk ; 8.043 ; 8.043 ; Rise ; sys_clk ;
-; sseg2[*] ; sys_clk ; 7.778 ; 7.778 ; Rise ; sys_clk ;
-; sseg2[0] ; sys_clk ; 8.155 ; 8.155 ; Rise ; sys_clk ;
-; sseg2[1] ; sys_clk ; 7.784 ; 7.784 ; Rise ; sys_clk ;
-; sseg2[2] ; sys_clk ; 7.778 ; 7.778 ; Rise ; sys_clk ;
-; sseg2[3] ; sys_clk ; 8.554 ; 8.554 ; Rise ; sys_clk ;
-; sseg2[4] ; sys_clk ; 8.452 ; 8.452 ; Rise ; sys_clk ;
-; sseg2[5] ; sys_clk ; 7.780 ; 7.780 ; Rise ; sys_clk ;
-; sseg2[6] ; sys_clk ; 8.264 ; 8.264 ; Rise ; sys_clk ;
-; sseg3[*] ; sys_clk ; 7.272 ; 7.272 ; Rise ; sys_clk ;
-; sseg3[0] ; sys_clk ; 7.689 ; 7.689 ; Rise ; sys_clk ;
-; sseg3[1] ; sys_clk ; 7.275 ; 7.275 ; Rise ; sys_clk ;
-; sseg3[2] ; sys_clk ; 7.274 ; 7.274 ; Rise ; sys_clk ;
-; sseg3[3] ; sys_clk ; 7.276 ; 7.276 ; Rise ; sys_clk ;
-; sseg3[4] ; sys_clk ; 7.720 ; 7.720 ; Rise ; sys_clk ;
-; sseg3[5] ; sys_clk ; 7.272 ; 7.272 ; Rise ; sys_clk ;
-; sseg3[6] ; sys_clk ; 7.876 ; 7.876 ; Rise ; sys_clk ;
-+-----------+------------+-------+-------+------------+-----------------+
-
-
-+-------------------------------------------------------------------+
-; Setup Transfers ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; sys_clk ; sys_clk ; 20970939 ; 0 ; 0 ; 0 ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
-+-------------------------------------------------------------------+
-; Hold Transfers ;
-+------------+----------+----------+----------+----------+----------+
-; From Clock ; To Clock ; RR Paths ; FR Paths ; RF Paths ; FF Paths ;
-+------------+----------+----------+----------+----------+----------+
-; sys_clk ; sys_clk ; 20970939 ; 0 ; 0 ; 0 ;
-+------------+----------+----------+----------+----------+----------+
-Entries labeled "false path" only account for clock-to-clock false paths and not path-based false paths. As a result, actual path counts may be lower than reported.
-
-
----------------
-; Report TCCS ;
----------------
-No dedicated SERDES Transmitter circuitry present in device or used in design
-
-
----------------
-; Report RSKM ;
----------------
-No dedicated SERDES Receiver circuitry present in device or used in design
-
-
-+------------------------------------------------+
-; Unconstrained Paths ;
-+---------------------------------+-------+------+
-; Property ; Setup ; Hold ;
-+---------------------------------+-------+------+
-; Illegal Clocks ; 0 ; 0 ;
-; Unconstrained Clocks ; 0 ; 0 ;
-; Unconstrained Input Ports ; 2 ; 2 ;
-; Unconstrained Input Port Paths ; 728 ; 728 ;
-; Unconstrained Output Ports ; 29 ; 29 ;
-; Unconstrained Output Port Paths ; 29 ; 29 ;
-+---------------------------------+-------+------+
-
-
-+------------------------------------+
-; TimeQuest Timing Analyzer Messages ;
-+------------------------------------+
-Info: *******************************************************************
-Info: Running Quartus II TimeQuest Timing Analyzer
- Info: Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
- Info: Processing started: Mon Dec 20 17:38:55 2010
-Info: Command: quartus_sta dt -c dt
-Info: qsta_default_script.tcl version: #1
-Critical Warning: Synopsys Design Constraints File file not found: 'dt.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
-Info: No user constrained base clocks found in the design. Calling "derive_clocks -period 1.0"
-Info: Deriving Clocks
- Info: create_clock -period 1.000 -name sys_clk sys_clk
-Critical Warning: Timing requirements not met
-Info: Worst-case setup slack is -20.245
- Info: Slack End Point TNS Clock
- Info: ========= ============= =====================
- Info: -20.245 -16040.760 sys_clk
-Info: Worst-case hold slack is 0.822
- Info: Slack End Point TNS Clock
- Info: ========= ============= =====================
- Info: 0.822 0.000 sys_clk
-Info: No Recovery paths to report
-Info: No Removal paths to report
-Info: Worst-case minimum pulse width slack is -2.003
- Info: Slack End Point TNS Clock
- Info: ========= ============= =====================
- Info: -2.003 -4074.623 sys_clk
-Info: The selected device family is not supported by the report_metastability command.
-Info: Design is not fully constrained for setup requirements
-Info: Design is not fully constrained for hold requirements
-Info: Quartus II TimeQuest Timing Analyzer was successful. 0 errors, 2 warnings
- Info: Peak virtual memory: 203 megabytes
- Info: Processing ended: Mon Dec 20 17:38:57 2010
- Info: Elapsed time: 00:00:02
- Info: Total CPU time (on all processors): 00:00:02
-
-
projects / calu.git / blobdiff