DT: DSE => f_max = 50.28MHz

[calu.git] / dt / DSE2.sdc

diff --git a/dt/DSE2.sdc b/dt/DSE2.sdc
new file mode 100644 (file)
index 0000000..229d30b
--- /dev/null
+++ b/dt/DSE2.sdc
@@ -0,0 +1,71 @@
+###########################################################################
+#
+# Generated by : Version 10.0 Build 262 08/18/2010 Service Pack 1 SJ Web Edition
+#
+# Project      : dt
+# Revision     : dt
+#
+# Date         : Thu Jan 13 17:54:53 CET 2011
+#
+###########################################################################
+
+
+#
+# ------------------------------------------
+#
+# Create generated clocks based on PLLs
+derive_pll_clocks -use_tan_name
+#
+# ------------------------------------------
+# WARNING: Global Fmax translated to derive_clocks. Behavior is not identical
+if {![info exist ::qsta_message_posted]} {
+    post_message -type warning "Original Global Fmax translated from QSF using derive_clocks"
+    set ::qsta_message_posted 1
+}
+derive_clocks -period "50 MHz"
+#
+
+
+# Original Clock Setting Name: sys_clk
+create_clock -period "20.000 ns" \
+             -name {sys_clk} {sys_clk}
+# ---------------------------------------------
+
+# ** Clock Latency
+#    -------------
+
+# ** Clock Uncertainty
+#    -----------------
+
+# ** Multicycles
+#    -----------
+# ** Cuts
+#    ----
+
+# ** Input/Output Delays
+#    -------------------
+
+
+
+
+# ** Tpd requirements
+#    ----------------
+
+# ** Setup/Hold Relationships
+#    ------------------------
+
+# ** Tsu/Th requirements
+#    -------------------
+
+
+# ** Tco/MinTco requirements
+#    -----------------------
+
+#
+# Entity Specific Timing Assignments found in
+# the Timing Analyzer Settings report panel
+#
+
+
+# ---------------------------------------------
+