signal sel_nxt, dmem_we, bus_rx :std_logic;
-
+signal calc_mem_res : gp_register_t;
begin
wb_reg_nxt.hword <= hword;
wb_reg_nxt.byte_s <= byte_s;
- regfile_val <= result; --(others => '0');
+ calc_mem_res <= result; --(others => '0');
if (wb_reg.dmem_en = '1' and wb_reg.dmem_write_en = '0') then -- ram read operation --alu_jmp = '0' and
- regfile_val <= data_ram_read;
+ calc_mem_res <= data_ram_read;
if (wb_reg.hword = '1') then
- regfile_val <= (others => '0');
+ calc_mem_res <= (others => '0');
if (wb_reg.address(1) = '1') then
- regfile_val(15 downto 0) <= data_ram_read(31 downto 16);
+ calc_mem_res(15 downto 0) <= data_ram_read(31 downto 16);
else
- regfile_val(15 downto 0) <= data_ram_read(15 downto 0);
+ calc_mem_res(15 downto 0) <= data_ram_read(15 downto 0);
end if;
end if;
if (wb_reg.byte_s = '1') then
- regfile_val <= (others => '0');
+ calc_mem_res <= (others => '0');
case wb_reg.address(1 downto 0) is
- when "00" => regfile_val(7 downto 0) <= data_ram_read(7 downto 0);
- when "01" => regfile_val(7 downto 0) <= data_ram_read(15 downto 8);
- when "10" => regfile_val(7 downto 0) <= data_ram_read(23 downto 16);
- when "11" => regfile_val(7 downto 0) <= data_ram_read(31 downto 24);
+ when "00" => calc_mem_res(7 downto 0) <= data_ram_read(7 downto 0);
+ when "01" => calc_mem_res(7 downto 0) <= data_ram_read(15 downto 8);
+ when "10" => calc_mem_res(7 downto 0) <= data_ram_read(23 downto 16);
+ when "11" => calc_mem_res(7 downto 0) <= data_ram_read(31 downto 24);
when others => null;
end case;
end if;
-out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt)
+out_logic: process(write_en, result_addr, wb_reg, alu_jmp, wb_reg_nxt, data_ram_read_ext, calc_mem_res)
begin
reg_we <= (write_en or (wb_reg.dmem_en and not(wb_reg.dmem_write_en))) and not(alu_jmp);
data_addr(DATA_ADDR_WIDTH+1 downto 0) <= wb_reg_nxt.address(DATA_ADDR_WIDTH+1 downto 0);
dmem_we <= wb_reg_nxt.dmem_write_en;
end if;
+
+ regfile_val <= calc_mem_res;
+
+ if (wb_reg.address(31 downto 4) = EXT_UART_ADDR) then
+ regfile_val <= data_ram_read_ext;
+ end if;
end process;
-addr_de_mult: process(wb_reg_nxt.address, ram_data, wb_reg,sel_nxt,wb_reg_nxt.dmem_write_en)
+addr_de_mult: process(wb_reg_nxt, ram_data, wb_reg,sel_nxt)
begin
+
ext_uart.sel <='0';
ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
ext_uart.byte_en <= (others => '0');
ext_gpmp.addr <= (others => '0');
-- wenn ich hier statt dem 4rer die konstante nehme dann gibts an fehler wegen nicht lokaler variable -.-
case wb_reg_nxt.address(31 downto 4) is
- when EXT_UART_ADDR =>
- ext_uart.sel <='1';
- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
- ext_uart.data <= ram_data;
- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
- case wb_reg_nxt.address(1 downto 0) is
- when "00" => ext_uart.byte_en <= "0001";
- when "01" => ext_uart.byte_en <= "0010";
- when "10" => ext_uart.byte_en <= "0100";
- --when "11" => ext_uart.byte_en <= "1000";
- when "11" => ext_uart.byte_en <= "1111";
- when others => null;
- end case;
+-- when EXT_UART_ADDR =>
+-- ext_uart.sel <='1';
+-- ext_uart.wr_en <= wb_reg_nxt.dmem_write_en;
+-- ext_uart.data <= ram_data;
+-- ext_uart.addr <= wb_reg_nxt.address(31 downto 2);
+-- case wb_reg_nxt.address(1 downto 0) is
+-- when "00" => ext_uart.byte_en <= "0001";
+-- when "01" => ext_uart.byte_en <= "0010";
+-- when "10" => ext_uart.byte_en <= "0100";
+-- --when "11" => ext_uart.byte_en <= "1000";
+-- when "11" => ext_uart.byte_en <= "1111";
+-- when others => null;
+-- end case;
when EXT_7SEG_ADDR =>
ext_7seg.sel <='1';