new_im_data_out
);
+ rem7seg: if "a" /= "a" generate
+
altera_7seg: if FPGATYPE /= "s3e" generate
sseg : extension_7seg
generic map(
port map(
clk,
reset,
- ext_7seg,
- sseg0,
- sseg1,
- sseg2,
- sseg3
+ --ext_7seg,
+ ext_7seg
+ --sseg0,
+ --sseg1,
+ --sseg2,
+ --sseg3
);
end generate;
+ end generate;
interrupt : extension_interrupt
generic map(