uart : es sendet !!!!

[calu.git] / cpu / src / r_w_ram_b.vhd

diff --git a/cpu/src/r_w_ram_b.vhd b/cpu/src/r_w_ram_b.vhd
index fa01d93b0dfd11a77b06eec9fea8fe634017b345..c995c109237913861106a9c3020ac2f45dfba914 100644 (file)
--- a/cpu/src/r_w_ram_b.vhd
+++ b/cpu/src/r_w_ram_b.vhd
@@ -14,22 +14,32 @@ architecture behaviour of r_w_ram is
 
        signal ram : RAM_TYPE := (
 
-       0 => "11101101000000000000000000000000",        --ldi
-       1 => "11101101001000000000000000000000",        --ldi
-       2 => "11100111101000000000000000000000",        --stw
-       3 => "11100001000000000000000000100001",
-       4 => "11101100100000000000001100000000",
-       5 => "00001011011111111111111010000011",
-       6 => "11101101000000000000000000001000",
-       7 => "11100111100000000000000000001111",
-       8 => "11100111100000000000000000010011",
-
-       9 => x"ed080048",       --;ldi r1, 9;;
-       10 => x"ed500080",      --;ldil r10, list@lo ;; global pointer
-       11 => x"fd500002",      --;ldih r10, list@hi;;
-       12 => x"eb000107",      --;call+ fibcall;;
+
+                       0 => "11101101000000000000000001011000", -- r0 = 11
+                       1 => "11101101000010000000000000111000", -- r1 = 7
+                       2 => "11100111100010000000000000000000", --stw
+                       3 => "11101101000000000000000000011000", -- r0 = 3
+                       4 => "11101101000010000000000001001000", -- r1 = 9
+                       5 => "11100111000010000000000000000000", --ldw
+                       6 => "11101101000000000000000000011000", -- r0 = 3
+                       7 => "11101101000010000000000001001000", -- r1 = 9
+                       --8 => "11100111100010000000000000000000", --stw
+--     0 => "11101101000000000000000000000000",        --ldi
+--     1 => "11101101001000000000000000000000",        --ldi
+--     2 => "11100111101000000000000000000000",        --stw
+--     3 => "11100001000000000000000000100001",
+--     4 => "11101100100000000000001100000000",
+--     5 => "00001011011111111111111010000011",
+--     6 => "11101101000000000000000000001000",
+--     7 => "11100111100000000000000000001111",
+--     8 => "11100111100000000000000000010011",
+
+--     9 => x"ed080048",       --;ldi r1, 9;;
+--     10 => x"ed500080",      --;ldil r10, list@lo ;; global pointer
+--     11 => x"fd500002",      --;ldih r10, list@hi;;
+--     12 => x"eb000107",      --;call+ fibcall;;
        --13 => x"eb7ffe03",    --;br+ main;;
-       13 => "11101011000000000000000000000010",       -- endless loop --2; fib(n) {
+--     13 => "11101011000000000000000000000010",       -- endless loop --2; fib(n) {
                        --2;   if (list[n] > 0) {
                        --2;    return list[n]
                        --2;   }
@@ -39,32 +49,32 @@ architecture behaviour of r_w_ram is
                        --2; }
                        --3;fibcall;
                        --2;update counter for aligned access
-       14 => x"e5088800",      --;lls r1, r1, 2 ;; *4
+--     14 => x"e5088800",      --;lls r1, r1, 2 ;; *4
                        --2;calculate adress of top element
-       15 => x"e0150800",      --;add r2, r10, r1;;
+--     15 => x"e0150800",      --;add r2, r10, r1;;
                        --3;fibmem;
                        --2;load top element
-       16 => x"e7010000",      --;ldw r0, 0(r2);;
+--     16 => x"e7010000",      --;ldw r0, 0(r2);;
                        --2;compare if set
-       17 => x"ec800000",      --;cmpi r0, 0;;
+--     17 => x"ec800000",      --;cmpi r0, 0;;
                        --2;return if set
-       18 => x"0b000008",      --;retnz-;;
+--     18 => x"0b000008",      --;retnz-;;
                        --2;decrement adress for next lopp
-       19 => x"e1910020",      --;subi r2, r2, 4;;
+--     19 => x"e1910020",      --;subi r2, r2, 4;;
                        --2;iterative call for n-1 element
-       20 => x"eb7ffe07",      --;call+ fibmem;;
+--     20 => x"eb7ffe07",      --;call+ fibmem;;
                        --2;load n-2 element
-       21 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
+--     21 => x"e7197ffc",      --;ldw r3, 0-4(r2);;
                        --2;add n-1 and n-2 element
-       22 => x"e0018000",      --;add r0, r3, r0;;
+--     22 => x"e0018000",      --;add r0, r3, r0;;
                        --2;increment address for n element
                        --2;is needed because after return
                        --2;we need r2 to be set to the address
                        --2;of element n
-       23 => x"e1110020",      --;addi r2, r2, 4;;
+--     23 => x"e1110020",      --;addi r2, r2, 4;;
                        --2;store fib n
-       24 => x"e7810000",      --;stw r0, 0(r2);;
-       25 => x"eb00000a",      --;ret+;;
+--     24 => x"e7810000",      --;stw r0, 0(r2);;
+--     25 => x"eb00000a",      --;ret+;;
 
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