VHDL Grundkonstrukt

[calu.git] / cpu / src / mem_pkg.vhd

diff --git a/cpu/src/mem_pkg.vhd b/cpu/src/mem_pkg.vhd
new file mode 100755 (executable)
index 0000000..cba7fd6
--- /dev/null
+++ b/cpu/src/mem_pkg.vhd
@@ -0,0 +1,84 @@
+library IEEE;
+
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+package mem_pkg is
+
+       component r_w_ram is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       wr_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       
+                       wr_en : in std_logic;
+                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+                       
+               --Output
+                       data_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+       end component r_w_ram;
+       
+       component r2_w_ram is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       
+                       wr_en : in std_logic;
+                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+                       
+               --Output
+                       data_out1, data_out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+       end component r2_w_ram;
+       
+       component rw2_ram is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       
+                       wr_en : in std_logic;
+                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+                       
+               --Output
+                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+       end component rw2_ram;
+       
+       component rw_ram is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       
+                       wr_en : in std_logic;
+                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+                       
+               --Output
+                       out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+       end component rw_ram;
+
+end package mem_pkg;