);
end component r2_w_ram;
- component rw2_ram is
+ component rw_r_ram is
generic (
ADDR_WIDTH : integer range 1 to integer'high;
DATA_WIDTH : integer range 1 to integer'high
--System inputs
clk : in std_logic;
--Input
- wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
-
- wr_en : in std_logic;
- data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
-
- --Output
- out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
- );
- end component rw2_ram;
-
- component rw_ram is
- generic (
- ADDR_WIDTH : integer range 1 to integer'high;
- DATA_WIDTH : integer range 1 to integer'high
- );
- port(
- --System inputs
- clk : in std_logic;
- --Input
- wr_addr, rd_addr1, rd_addr2 : in std_logic_vector(ADDR_WIDTH-1 downto 0);
+ rw_addr, rd_addr : in std_logic_vector(ADDR_WIDTH-1 downto 0);
wr_en : in std_logic;
data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
--Output
- out1, out2: out std_logic_vector(DATA_WIDTH-1 downto 0)
+ rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
);
- end component rw_ram;
+ end component rw_r_ram;
end package mem_pkg;