uart : es sendet !!!!

[calu.git] / cpu / src / extension_uart_pkg.vhd

diff --git a/cpu/src/extension_uart_pkg.vhd b/cpu/src/extension_uart_pkg.vhd
index fb839ffc5476682aad0baa802667f5bd76996fe4..604a06057e810c154d36f887fa81550219854bd4 100644 (file)
--- a/cpu/src/extension_uart_pkg.vhd
+++ b/cpu/src/extension_uart_pkg.vhd
@@ -4,44 +4,20 @@ use IEEE.std_logic_1164.all;
 use IEEE.numeric_std.all;
 
 use work.common_pkg.all;
-
+use work.extension_pkg.all;
 
 package extension_uart_pkg is
 
-constant EXTWORDL : integer := log2c(4);
-constant BYTEADDR : integer := log2c(4);
-constant PCOUNT   : integer := 3;
-constant EXTWORDS : integer := EXTWORDL + BYTEADDR;
-
-subtype ext_addrid_t  is std_logic_vector(gp_register_t'high - EXTWORDS downto 0);
-subtype ext_addr_t    is std_logic_vector((gp_register_t'high-BYTEADDR) downto 0);    
-subtype paddr_t is std_logic_vector(log2c(PCOUNT)-1 downto 0);   
-
-        type extmod_rec is record
-                sel   : std_logic;
-                wr_en : std_logic;
-                byte_en : std_logic_vector(gp_register_t'length/byte_t'length-1 downto 0); 
-                data : gp_register_t;
-                addr : ext_addr_t;     
-        end record; 
-
-
-type status_rec is record
-               zero : std_logic;
-               oflo : std_logic;
-               sign : std_logic;
-               carry : std_logic;
-end record;
-
-constant EXT_7SEG_ADDR:   ext_addrid_t := x"FFFFFFA";
-constant EXT_EXTMEM_ADDR: ext_addrid_t := x"FFFFFFB";
-constant EXT_TIMER_ADDR:  ext_addrid_t := x"FFFFFFC";
-constant EXT_AC97_ADDR:   ext_addrid_t := x"FFFFFFD";
-constant EXT_UART_ADDR:   ext_addrid_t := x"FFFFFFE";
-constant EXT_GPMP_ADDR:    ext_addrid_t := x"FFFFFFF";
+
+
+
+
+
 --RS232
 constant UART_WIDTH : integer := 8;
 subtype uart_data is std_logic_vector(UART_WIDTH-1 downto 0);
+constant BAUD_RATE_WITH : integer := 16;
+subtype baud_rate_l is std_logic_vector(BAUD_RATE_WITH-1 downto 0);
 --CLKs
 constant CLK_FREQ_MHZ : real := 33.33;
 constant BAUD_RATE : integer := 115200;
@@ -68,6 +44,10 @@ constant CLK_PER_BAUD : integer := integer((CLK_FREQ_MHZ * 1000000.0) / real(BAU
  end component extension_uart;
 
 component rs232_tx is
+       generic (
+               -- active reset value
+               RESET_VALUE : std_logic
+               );
 
        port(
                --System inputs
@@ -80,8 +60,10 @@ component rs232_tx is
                --From/to sendlogic
                new_tx_data : in std_logic;
                tx_data : in uart_data;
-               tx_rdy : out std_logic
-       );
+               tx_rdy : out std_logic;
+               bd_rate : in baud_rate_l;
+               stop_bit : in std_logic 
+);
 end component rs232_tx;
 
 end package extension_uart_pkg;