VHDL Grundkonstrukt

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
new file mode 100644 (file)
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+++ b/cpu/src/execute_stage_b.vhd
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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+use work.core_pkg.all;
+
+architecture behav of execute_stage is
+
+
+begin
+
+syn: process(sys_clk, reset)
+
+begin
+
+       if (reset = RESET_VALUE) then
+                               
+       elsif rising_edge(sys_clk) then
+               
+       end if;
+       
+end process; 
+
+end behav;
+