pipeline erste version mit 31bit shifter (kostet 7MHz und viele LEs)

[calu.git] / cpu / src / execute_stage_b.vhd

diff --git a/cpu/src/execute_stage_b.vhd b/cpu/src/execute_stage_b.vhd
index 1f2c194ac263470f6bfa560da6ae9c9abd1bdfb9..5979a8b048b917574ddc48f5ac5a6efb3ee51e2f 100644 (file)
--- a/cpu/src/execute_stage_b.vhd
+++ b/cpu/src/execute_stage_b.vhd
@@ -51,7 +51,7 @@ begin
        
 end process;
 
-asyn: process(reset,dec_instr, alu_nxt, psw)
+asyn: process(reset,dec_instr, alu_nxt, psw, reg)
 begin
 
         condition <= dec_instr.condition;