VHDL Grundkonstrukt

[calu.git] / cpu / src / execute_stage.vhd

diff --git a/cpu/src/execute_stage.vhd b/cpu/src/execute_stage.vhd
new file mode 100644 (file)
index 0000000..d69fdc0
--- /dev/null
+++ b/cpu/src/execute_stage.vhd
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+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity execute_stage is
+
+       generic (
+                       -- active reset value
+                       RESET_VALUE : std_logic;
+                       -- active logic value
+                       LOGIC_ACT : std_logic;
+                       
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+                       reset : in std_logic;
+               );
+               
+end execute_stage;