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[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index d81095c664d43b01cdaa528d893979df97c91434..5352332ddcc9744162ed4eaefa41bf07ea3bdc04 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -59,6 +59,7 @@ architecture behav of core_top is
                 signal gpm_out_pin : gp_register_t;
                 signal nop_pin : std_logic;
 
+                signal vers, vers_nxt : exec2wb_rec;
 
 begin
 
@@ -117,14 +118,54 @@ begin
                 port map(sys_clk, sys_res,to_next_stage, reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, gpm_in_pin, result_pin, result_addr_pin,addr_pin,
                 data_pin, alu_jump_pin,brpr_pin, wr_en_pin, dmem_pin,dmem_wr_en_pin,hword_pin,byte_s_pin, gpm_out_pin);
 
-          writeback_st : writeback_stage
+
+                       vers_nxt.result <= result_pin;
+                       vers_nxt.result_addr <= result_addr_pin;
+                       vers_nxt.address <= addr_pin;
+                       vers_nxt.ram_data <= data_pin;
+                       vers_nxt.alu_jmp <= alu_jump_pin;
+                       vers_nxt.br_pred <= brpr_pin;
+                       vers_nxt.write_en <= wr_en_pin;
+                       vers_nxt.dmem_en <= dmem_pin;
+                       vers_nxt.dmem_write_en <= dmem_wr_en_pin;
+                       vers_nxt.hword <= hword_pin;
+                       vers_nxt.byte_s <= byte_s_pin;
+                                                                        
+--          writeback_st : writeback_stage
+--                generic map('0', '1')
+--                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
+--                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+--                reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
+--
+
+                       writeback_st : writeback_stage
                 generic map('0', '1')
-                port map(sys_clk, sys_res, result_pin, result_addr_pin, addr_pin, data_pin, alu_jump_pin, brpr_pin, 
-                wr_en_pin, dmem_pin, dmem_wr_en_pin, hword_pin, byte_s_pin,
+                port map(sys_clk, sys_res, vers.result, vers.result_addr, vers.address, vers.ram_data, vers.alu_jmp, vers.br_pred, 
+                vers.write_en, vers.dmem_en, vers.dmem_write_en, vers.hword, vers.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, sseg0, sseg1, sseg2, sseg3);
 
 
+syn: process(sys_clk, sys_res)
 
+begin
+
+       if sys_res = '0' then
+                       vers.result <= (others => '0');
+                       vers.result_addr <= (others => '0');
+                       vers.address <= (others => '0');
+                       vers.ram_data <= (others => '0');
+                       vers.alu_jmp <= '0';
+                       vers.br_pred <= '0';
+                       vers.write_en <= '0';
+                       vers.dmem_en <= '0';
+                       vers.dmem_write_en <= '0';
+                       vers.hword <= '0';
+                       vers.byte_s <= '0';
+       elsif rising_edge(sys_clk) then
+               vers <= vers_nxt;
+       end if;
+       
+end process;
 
                
 --init : process(all)
@@ -145,4 +186,5 @@ begin
 --     sys_res <= '1';
 
 --     reg_wr_data <= reg_wr_data_pin;
+
 end behav;