dt: baudrate an PLL (50MHz) angepasst

[calu.git] / cpu / src / core_top.vhd

diff --git a/cpu/src/core_top.vhd b/cpu/src/core_top.vhd
index a8d3bde57bfbc280729be3cd777bf3733779c9bf..531ccd1b43f9b6027076d9aaedbb58b5ff699ed7 100644 (file)
--- a/cpu/src/core_top.vhd
+++ b/cpu/src/core_top.vhd
@@ -174,7 +174,7 @@ begin
 --
 
                        writeback_st : writeback_stage
-                generic map('0', '1', "altera", 2083)
+                generic map('0', '1', "altera", 5208)
                 port map(sys_clk, sys_res_n and soft_res_n, vers_nxt.result, vers_nxt.result_addr, vers_nxt.address, vers_nxt.ram_data, vers_nxt.alu_jmp, vers_nxt.br_pred, 
                 vers_nxt.write_en, vers_nxt.dmem_en, vers_nxt.dmem_write_en, vers_nxt.hword, vers_nxt.byte_s,
                 reg_wr_data_pin, reg_we_pin, reg_w_addr_pin, jump_result_pin, alu_jump_bit_pin,bus_tx, bus_rx,