--System inputs
clk : in std_logic;
reset : in std_logic;
-
+
--Data inputs
jump_result : in instruction_addr_t;
prediction_result : in instruction_addr_t;
alu_jump_bit : in std_logic;
--Data outputs
- instruction : out instruction_word_t
-
+ instruction : out instruction_word_t;
+ prog_cnt : out instruction_addr_t
);
end component fetch_stage;
--Data inputs
instruction : in instruction_word_t;
+ prog_cnt : in instruction_addr_t;
reg_w_addr : in std_logic_vector(REG_ADDR_WIDTH-1 downto 0);
reg_wr_data : in gp_register_t;
reg_we : in std_logic;
-- reg2_rd_data : out gp_register_t;
branch_prediction_res : out instruction_word_t;
branch_prediction_bit : out std_logic;
+
to_next_stage : out dec_op
);
end component decode_stage;