when LDST_OP =>\r
res_prod := '0';\r
mem_op := '1';\r
- right_o <= displacement;\r
+ --right_o <= displacement;\r
+ addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));\r
if op_detail(IMM_OPT) = '1' then\r
result_v.result := right_operand;\r
res_prod := '1';\r