--right_o <= displacement;
addr <= std_logic_vector(unsigned(left_operand)+unsigned(displacement));
if op_detail(IMM_OPT) = '1' then
- result_v.result := right_operand;
+
+ result_v.result := right_operand;
+
+ if (op_detail(LDI_REPLACE_OPT) = '0') then
+ result_v.result := left_operand;
+ if (op_detail(LOW_HIGH_OPT) = '1') then
+ result_v.result(31 downto 16) := right_operand(31 downto 16);
+ else
+ result_v.result(15 downto 0) := right_operand(15 downto 0);
+ end if;
+ end if;
+
res_prod := '1';
mem_op := '0';
addr(DATA_ADDR_WIDTH + 2) <= '0';