* ARM codegen update;

svn path=/trunk/mono/; revision=14043

diff --git a/mono/arch/arm/arm-codegen.c b/mono/arch/arm/arm-codegen.c
index 88d572afe132013f330de34b74f179a4e4839f08..9914ace34f3049abe17d473f926878dba9770980 100644 (file)
--- a/mono/arch/arm/arm-codegen.c
+++ b/mono/arch/arm/arm-codegen.c
@@ -156,9 +156,9 @@ arminstr_t* arm_mov_reg_imm32_cond(arminstr_t* p, int reg, armword_t imm32, int
 
        if ((shift & 0x80000001) != 1) {
                if (shift >= 0) {
-                       ARM_MOV_REG_IMM_COND(p, reg, imm32 >> ((32 - shift) & 31), shift >> 1, cond);
+                       ARM_MOV_REG_IMM_COND(p, reg, imm32 >> ((32 - shift) & 31), shift, cond);
                } else {
-                       ARM_MVN_REG_IMM_COND(p, reg, (imm32 ^ (~0)) >> ((32 + 2 + shift) & 31), (-shift - 2) >> 1, cond);
+                       ARM_MVN_REG_IMM_COND(p, reg, (imm32 ^ (~0)) >> ((32 + 2 + shift) & 31), (-shift - 2), cond);
                }
        } else {
                mov_op = ARMOP_MOV;
@@ -172,12 +172,12 @@ arminstr_t* arm_mov_reg_imm32_cond(arminstr_t* p, int reg, armword_t imm32, int
 
                shift = (arm_bsf(imm32) - 1) & (~1);
                snip = imm32 & (0xFF << shift);
-               ARM_EMIT(p, ARM_DEF_DPI_IMM_COND(snip >> shift, (32 - shift) >> 1, reg, 0, 0, mov_op, cond));
+               ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((unsigned)snip >> shift, (32 - shift) >> 1, reg, 0, 0, mov_op, cond));
 
                while ((imm32 ^= snip) != 0) {
                        shift = (arm_bsf(imm32) - 1) & (~1);
                        snip = imm32 & (0xFF << shift);
-                       ARM_EMIT(p, ARM_DEF_DPI_IMM_COND(snip >> shift, (32 - shift) >> 1, reg, reg, 0, step_op, cond));
+                       ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((unsigned)snip >> shift, (32 - shift) >> 1, reg, reg, 0, step_op, cond));
                }
        }
 

diff --git a/mono/arch/arm/arm-codegen.h b/mono/arch/arm/arm-codegen.h
index 3d6c7988a60769e05e81d2c7667e7da5bfb2ab4c..61302a43937aad9748cf535796cf62f43a371e6f 100644 (file)
--- a/mono/arch/arm/arm-codegen.h
+++ b/mono/arch/arm/arm-codegen.h
@@ -31,7 +31,13 @@ arminstr_t* arm_mov_reg_imm32(arminstr_t* p, int reg, armword_t imm32);
        void __inline _arm_emit(arminstr_t** p, arminstr_t i) {**p = i; (*p)++;}
 #      define ARM_EMIT(p, i) _arm_emit((arminstr_t**)&p, (arminstr_t)(i))
 #else
-#      define ARM_EMIT(p, i) *(arminstr_t*)p = (arminstr_t)i; ((arminstr_t*)p)++
+#      define ARM_EMIT(p, i) do {*(arminstr_t*)p = (arminstr_t)i; ((arminstr_t*)p)++;} while (0)
+#endif
+
+#if defined(_MSC_VER) && !defined(ARM_NOIASM)
+#      define ARM_IASM(_expr) __emit (_expr)
+#else
+#      define ARM_IASM(_expr) 
 #endif
 
 /* even_scale = rot << 1 */
@@ -98,6 +104,9 @@ typedef enum {
        ARMREG_CR14,
        ARMREG_CR15,
 
+       /* XScale: acc0 on CP0 */
+       ARMREG_ACC0 = ARMREG_CR0,
+
        ARMREG_MAX = ARMREG_R15
 } ARMReg;
 
@@ -110,22 +119,22 @@ typedef enum {
 
 
 typedef enum {
-       ARMCOND_EQ = 0x0,          /* Equal */
-       ARMCOND_NE = 0x1,          /* Not equal, or unordered */
-       ARMCOND_CS = 0x2,          /* Carry set */
-       ARMCOND_HS = ARMCOND_CS,   /* Unsigned higher or same */
-       ARMCOND_CC = 0x3,          /* Carry clear */
+       ARMCOND_EQ = 0x0,          /* Equal; Z = 1 */
+       ARMCOND_NE = 0x1,          /* Not equal, or unordered; Z = 0 */
+       ARMCOND_CS = 0x2,          /* Carry set; C = 1 */
+       ARMCOND_HS = ARMCOND_CS,   /* Unsigned higher or same; */
+       ARMCOND_CC = 0x3,          /* Carry clear; C = 0 */
        ARMCOND_LO = ARMCOND_CC,   /* Unsigned lower */
-       ARMCOND_MI = 0x4,          /* Negative */
-       ARMCOND_PL = 0x5,          /* Positive or zero */
-       ARMCOND_VS = 0x6,          /* Overflow */
-       ARMCOND_VC = 0x7,          /* No overflow */
-       ARMCOND_HI = 0x8,          /* Unsigned higher */
-       ARMCOND_LS = 0x9,          /* Unsigned lower or same */
-       ARMCOND_GE = 0xA,          /* Signed greater than or equal */
-       ARMCOND_LT = 0xB,          /* Signed less than */
-       ARMCOND_GT = 0xC,          /* Signed greater than */
-       ARMCOND_LE = 0xD,          /* Signed less than or equal */
+       ARMCOND_MI = 0x4,          /* Negative; N = 1 */
+       ARMCOND_PL = 0x5,          /* Positive or zero; N = 0 */
+       ARMCOND_VS = 0x6,          /* Overflow; V = 1 */
+       ARMCOND_VC = 0x7,          /* No overflow; V = 0 */
+       ARMCOND_HI = 0x8,          /* Unsigned higher; C = 1 && Z = 0 */
+       ARMCOND_LS = 0x9,          /* Unsigned lower or same; C = 0 || Z = 1 */
+       ARMCOND_GE = 0xA,          /* Signed greater than or equal; N = V */
+       ARMCOND_LT = 0xB,          /* Signed less than; N != V */
+       ARMCOND_GT = 0xC,          /* Signed greater than; Z = 0 && N = V */
+       ARMCOND_LE = 0xD,          /* Signed less than or equal; Z = 1 && N != V */
        ARMCOND_AL = 0xE,          /* Always */
        ARMCOND_NV = 0xF,          /* Never */
 
@@ -185,12 +194,41 @@ typedef enum {
        ARMOP_MLA   = 0x1, /* Rd := (Rm*Rs)+Rn */
 
        /* ARM3M+ */
-       ARMOP_UMUL  = 0x4,
+       ARMOP_UMULL = 0x4,
        ARMOP_UMLAL = 0x5,
        ARMOP_SMULL = 0x6,
-       ARMOP_SMLAL = 0x7
+       ARMOP_SMLAL = 0x7,
+
+       /* for data transfers with register offset */
+       ARM_UP   = 1,
+       ARM_DOWN = 0
 } ARMOpcode;
 
+typedef enum {
+       THUMBOP_AND  = 0,
+       THUMBOP_EOR  = 1,
+       THUMBOP_LSL  = 2,
+       THUMBOP_LSR  = 3,
+       THUMBOP_ASR  = 4,
+       THUMBOP_ADC  = 5,
+       THUMBOP_SBC  = 6,
+       THUMBOP_ROR  = 7,
+       THUMBOP_TST  = 8,
+       THUMBOP_NEG  = 9,
+       THUMBOP_CMP  = 10,
+       THUMBOP_CMN  = 11,
+       THUMBOP_ORR  = 12,
+       THUMBOP_MUL  = 13,
+       THUMBOP_BIC  = 14,
+       THUMBOP_MVN  = 15,
+       THUMBOP_MOV  = 16,
+       THUMBOP_CMPI = 17,
+       THUMBOP_ADD  = 18,
+       THUMBOP_SUB  = 19,
+       THUMBOP_CMPH = 19,
+       THUMBOP_MOVH = 20
+} ThumbOpcode;
+
 
 /* Generic form - all ARM instructions are conditional. */
 typedef struct {
@@ -295,12 +333,18 @@ typedef union {
 #define ARM_DEF_DPI_IMM(imm8, rot, rd, rn, s, op) \
        ARM_DEF_DPI_IMM_COND(imm8, rot, rd, rn, s, op, ARMCOND_AL)
 
-
+/* codegen */
 #define ARM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
        ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
 #define ARM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
        ARM_EMIT(p, ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
 
+/* inline */
+#define ARM_IASM_DPIOP_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
+       ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 0, (op), cond))
+#define ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(p, op, rd, rn, imm8, rot, cond) \
+       ARM_IASM(ARM_DEF_DPI_IMM_COND((imm8), ((rot) >> 1), (rd), (rn), 1, (op), cond))
+
 
 
 #define ARM_DEF_DPI_REG_IMMSHIFT_COND(rm, shift_type, imm_shift, rd, rn, s, op, cond) \
@@ -314,6 +358,7 @@ typedef union {
        (ARM_DPI_TAG)               | \
        ARM_DEF_COND(cond)
 
+/* codegen */
 #define ARM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
        ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
 
@@ -326,7 +371,46 @@ typedef union {
 #define ARM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
        ARM_EMIT(p, ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
 
+/* inline */
+#define ARM_IASM_DPIOP_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
+       ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 0, (op), cond))
 
+#define ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(p, op, rd, rn, rm, shift_t, imm_shift, cond) \
+       ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), shift_t, imm_shift, (rd), (rn), 1, (op), cond))
+
+#define ARM_IASM_DPIOP_REG_REG_COND(p, op, rd, rn, rm, cond) \
+       ARM_IASM(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 0, (op), cond))
+
+#define ARM_IASM_DPIOP_S_REG_REG_COND(p, op, rd, rn, rm, cond) \
+       ARM_IASM_EMIT(ARM_DEF_DPI_REG_IMMSHIFT_COND((rm), ARMSHIFT_LSL, 0, (rd), (rn), 1, (op), cond))
+
+
+/* Rd := Rn op (Rm shift_type Rs) */
+#define ARM_DEF_DPI_REG_REGSHIFT_COND(rm, shift_type, rs, rd, rn, s, op, cond) \
+       (rm)                        | \
+       (1 << 4)                    | \
+       ((shift_type & 3) << 5)     | \
+       ((rs) << 8)                 | \
+       ((rd) << 12)                | \
+       ((rn) << 16)                | \
+       ((s) << 20)                 | \
+       ((op) << 21)                | \
+       (ARM_DPI_TAG)               | \
+       ARM_DEF_COND(cond)
+
+/* codegen */
+#define ARM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
+       ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
+
+#define ARM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
+       ARM_EMIT(p, ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
+
+/* inline */
+#define ARM_IASM_DPIOP_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
+       ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 0, (op), cond))
+
+#define ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(p, op, rd, rn, rm, shift_t, rs, cond) \
+       ARM_IASM(ARM_DEF_DPI_REG_REGSHIFT_COND((rm), shift_t, (rs), (rd), (rn), 1, (op), cond))
 
 
 
@@ -348,27 +432,47 @@ typedef struct {
 #define ARM_MRT_TAG ARM_MRT_ID << 25
 
 #define ARM_DEF_MRT(regs, rn, l, w, s, u, p, cond) \
-               (regs)        | \
-               (rn << 16)    | \
-               (l << 20)     | \
-               (w << 21)     | \
-               (s << 22)     | \
-               (u << 23)     | \
-               (p << 24)     | \
-               (ARM_MRT_TAG) | \
-               ARM_DEF_COND(cond)
+       (regs)        | \
+       (rn << 16)    | \
+       (l << 20)     | \
+       (w << 21)     | \
+       (s << 22)     | \
+       (u << 23)     | \
+       (p << 24)     | \
+       (ARM_MRT_TAG) | \
+       ARM_DEF_COND(cond)
 
 
 
 /* stmdb sp!, {regs} */
 #define ARM_PUSH(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
+#define ARM_IASM_PUSH(regs) ARM_IASM(ARM_DEF_MRT(regs, ARMREG_SP, 0, 1, 0, 0, 1, ARMCOND_AL))
 
 /* ldmia sp!, {regs} */
 #define ARM_POP(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
+#define ARM_IASM_POP(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 1, 0, 1, 0, ARMCOND_AL))
 
 /* ldmia sp, {regs} ; (no write-back) */
 #define ARM_POP_NWB(p, regs) ARM_EMIT(p, ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
-
+#define ARM_IASM_POP_NWB(regs) ARM_IASM_EMIT(ARM_DEF_MRT(regs, ARMREG_SP, 1, 0, 0, 1, 0, ARMCOND_AL))
+
+#define ARM_PUSH1(p, r1) ARM_PUSH(p, (1 << r1))
+#define ARM_PUSH2(p, r1, r2) ARM_PUSH(p, (1 << r1) | (1 << r2))
+#define ARM_PUSH3(p, r1, r2, r3) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3))
+#define ARM_PUSH4(p, r1, r2, r3, r4) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
+#define ARM_PUSH5(p, r1, r2, r3, r4, r5) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
+#define ARM_PUSH6(p, r1, r2, r3, r4, r5, r6) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
+#define ARM_PUSH7(p, r1, r2, r3, r4, r5, r6, r7) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
+#define ARM_PUSH8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_PUSH(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
+
+#define ARM_POP8(p, r1, r2, r3, r4, r5, r6, r7, r8) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7) | (1 << r8))
+#define ARM_POP7(p, r1, r2, r3, r4, r5, r6, r7) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6) | (1 << r7))
+#define ARM_POP6(p, r1, r2, r3, r4, r5, r6) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5) | (1 << r6))
+#define ARM_POP5(p, r1, r2, r3, r4, r5) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4) | (1 << r5))
+#define ARM_POP4(p, r1, r2, r3, r4) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3) | (1 << r4))
+#define ARM_POP3(p, r1, r2, r3) ARM_POP(p, (1 << r1) | (1 << r2) | (1 << r3))
+#define ARM_POP2(p, r1, r2) ARM_POP(p, (1 << r1) | (1 << r2))
+#define ARM_POP1(p, r1) ARM_POP(p, (1 << r1))
 
 
 /* Multiply instructions */
@@ -389,6 +493,60 @@ typedef struct {
 #define ARM_MUL_MASK ((0xF << 24) | (0xF << 4))
 #define ARM_MUL_TAG ((ARM_MUL_ID << 24) | (ARM_MUL_ID2 << 4))
 
+#define ARM_DEF_MUL_COND(op, rd, rm, rs, rn, s, cond) \
+       (rm)             | \
+       ((rs) << 8)      | \
+       ((rn) << 12)     | \
+       ((rd) << 16)     | \
+       ((s & 1) << 17)  | \
+       ((op & 7) << 18) | \
+       ARM_MUL_TAG      | \
+       ARM_DEF_COND(cond)
+
+/* Rd := (Rm * Rs)[31:0]; 32 x 32 -> 32 */
+#define ARM_MUL_COND(p, rd, rm, rs, cond) \
+       ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
+#define ARM_MUL(p, rd, rm, rs) \
+       ARM_MUL_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_MULS_COND(p, rd, rm, rs, cond) \
+       ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
+#define ARM_MULS(p, rd, rm, rs) \
+       ARM_MULS_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_MUL_REG_REG(p, rd, rm, rs) ARM_MUL(p, rd, rm, rs)
+#define ARM_MULS_REG_REG(p, rd, rm, rs) ARM_MULS(p, rd, rm, rs)
+
+/* inline */
+#define ARM_IASM_MUL_COND(rd, rm, rs, cond) \
+       ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 0, cond))
+#define ARM_IASM_MUL(rd, rm, rs) \
+       ARM_IASM_MUL_COND(rd, rm, rs, ARMCOND_AL)
+#define ARM_IASM_MULS_COND(rd, rm, rs, cond) \
+       ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MUL, rd, rm, rs, 0, 1, cond))
+#define ARM_IASM_MULS(rd, rm, rs) \
+       ARM_IASM_MULS_COND(rd, rm, rs, ARMCOND_AL)
+
+
+/* Rd := (Rm * Rs) + Rn; 32x32+32->32 */
+#define ARM_MLA_COND(p, rd, rm, rs, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
+#define ARM_MLA(p, rd, rm, rs, rn) \
+       ARM_MLA_COND(p, rd, rm, rs, rn, ARMCOND_AL)
+#define ARM_MLAS_COND(p, rd, rm, rs, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
+#define ARM_MLAS(p, rd, rm, rs, rn) \
+       ARM_MLAS_COND(p, rd, rm, rs, rn, ARMCOND_AL)
+
+/* inline */
+#define ARM_IASM_MLA_COND(rd, rm, rs, rn, cond) \
+       ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 0, cond))
+#define ARM_IASM_MLA(rd, rm, rs, rn) \
+       ARM_IASM_MLA_COND(rd, rm, rs, rn, ARMCOND_AL)
+#define ARM_IASM_MLAS_COND(rd, rm, rs, rn, cond) \
+       ARM_IASM_EMIT(ARM_DEF_MUL_COND(ARMOP_MLA, rd, rm, rs, rn, 1, cond))
+#define ARM_IASM_MLAS(rd, rm, rs, rn) \
+       ARM_IASM_MLAS_COND(rd, rm, rs, rn, ARMCOND_AL)
+
+
 
 /*  Word/byte transfer */
 typedef union {
@@ -400,7 +558,7 @@ typedef union {
                arminstr_t ls      :  1;
                arminstr_t wb      :  1;
                arminstr_t b       :  1;
-               arminstr_t u       :  1;
+               arminstr_t u       :  1; /* down(0) / up(1) */
                arminstr_t p       :  1; /* post-index(0) / pre-index(1) */
                arminstr_t type    :  1; /* imm(0) / register(1) */
                arminstr_t tag     :  2; /* 0 1 */
@@ -427,7 +585,7 @@ typedef union {
 
 #define ARM_WXFER_MAX_OFFS 0xFFF
 
-/* this macro checks imm12 bounds */
+/* this macro checks for imm12 bounds */
 #define ARM_EMIT_WXFER_IMM(ptr, imm12, rd, rn, ls, wb, b, p, cond) \
        do { \
                int _imm12 = (int)(imm12) < -ARM_WXFER_MAX_OFFS  \
@@ -487,9 +645,13 @@ typedef union {
 
 #define ARM_STRB_IMM(p, rd, rn, imm) ARM_STRB_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
 
+/* write-back */
+#define ARM_STR_IMM_WB_COND(p, rd, rn, imm, cond) \
+       ARM_EMIT_WXFER_IMM(p, imm, rd, rn, ARMOP_STR, 1, 0, 1, cond)
+#define ARM_STR_IMM_WB(p, rd, rn, imm) ARM_STR_IMM_WB_COND(p, rd, rn, imm, ARMCOND_AL)
 
 
-#define ARM_DEF_WXFER_REG_REG(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
+#define ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, u, p, cond) \
        (rm)                | \
        ((shift_type) << 5) | \
        ((shift) << 7)      | \
@@ -498,21 +660,49 @@ typedef union {
        ((ls) << 20)        | \
        ((wb) << 21)        | \
        ((b)  << 22)        | \
-       ((p) << 24)         | \
-       (1 << 25)           | \
+       ((u)  << 23)        | \
+       ((p)  << 24)        | \
+       (1    << 25)        | \
        ARM_WXFER_TAG       | \
        ARM_DEF_COND(cond)
 
+#define ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
+       ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_UP, p, cond)
+#define ARM_DEF_WXFER_REG_MINUS_REG_COND(rm, shift_type, shift, rd, rn, ls, wb, b, p, cond) \
+       ARM_DEF_WXFER_REG_REG_UPDOWN_COND(rm, shift_type, shift, rd, rn, ls, wb, b, ARM_DOWN, p, cond)
+
 
 #define ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
-       ARM_EMIT(p, ARM_DEF_WXFER_REG_REG(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
+       ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 0, 1, cond))
 #define ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
        ARM_LDR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
 #define ARM_LDR_REG_REG(p, rd, rn, rm) \
        ARM_LDR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
 
-
-
+#define ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
+       ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_LDR, 0, 1, 1, cond))
+#define ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
+       ARM_LDRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
+#define ARM_LDRB_REG_REG(p, rd, rn, rm) \
+       ARM_LDRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
+
+#define ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
+       ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 0, 1, cond))
+#define ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
+       ARM_STR_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
+#define ARM_STR_REG_REG(p, rd, rn, rm) \
+       ARM_STR_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
+
+/* zero-extend */
+#define ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, cond) \
+       ARM_EMIT(p, ARM_DEF_WXFER_REG_REG_COND(rm, shift_type, shift, rd, rn, ARMOP_STR, 0, 1, 1, cond))
+#define ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, shift_type, shift) \
+       ARM_STRB_REG_REG_SHIFT_COND(p, rd, rn, rm, shift_type, shift, ARMCOND_AL)
+#define ARM_STRB_REG_REG(p, rd, rn, rm) \
+       ARM_STRB_REG_REG_SHIFT(p, rd, rn, rm, ARMSHIFT_LSL, 0)
+
+
+/* ARMv4+ */
 /* Half-word or byte (signed) transfer. */
 typedef struct {
        arminstr_t rm     : 4; /* imm_lo */
@@ -573,6 +763,43 @@ typedef struct {
        ARM_STRH_IMM_COND(p, rd, rn, imm, ARMCOND_AL)
 
 
+#define ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, u, p, cond) \
+       ((rm) & 0xF)                | \
+       ((h) << 5)                  | \
+       ((s) << 6)                  | \
+       ((rd) << 12)                | \
+       ((rn) << 16)                | \
+       ((ls) << 20)                | \
+       ((wb) << 21)                | \
+       (0 << 22)                   | \
+       ((u) << 23)                 | \
+       ((p) << 24)                 | \
+       ARM_HXFER_TAG               | \
+       ARM_DEF_COND(cond)
+
+#define ARM_DEF_HXFER_REG_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
+       ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_UP, p, cond)
+#define ARM_DEF_HXFER_REG_MINUS_REG_COND(rm, h, s, rd, rn, ls, wb, p, cond) \
+       ARM_DEF_HXFER_REG_REG_UPDOWN_COND(rm, h, s, rd, rn, ls, wb, ARM_DOWN, p, cond)
+
+#define ARM_LDRH_REG_REG_COND(p, rm, rd, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_LDR, 0, 1, cond))
+#define ARM_LDRH_REG_REG(p, rm, rd, rn) \
+       ARM_LDRH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
+#define ARM_LDRSH_REG_REG_COND(p, rm, rd, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
+#define ARM_LDRSH_REG_REG(p, rm, rd, rn) \
+       ARM_LDRSH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
+#define ARM_LDRSB_REG_REG_COND(p, rm, rd, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 0, 1, rd, rn, ARMOP_LDR, 0, 1, cond))
+#define ARM_LDRSB_REG_REG(p, rm, rd, rn) ARM_LDRSB_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
+
+#define ARM_STRH_REG_REG_COND(p, rm, rd, rn, cond) \
+       ARM_EMIT(p, ARM_DEF_HXFER_REG_REG_COND(rm, 1, 0, rd, rn, ARMOP_STR, 0, 1, cond))
+#define ARM_STRH_REG_REG(p, rm, rd, rn) \
+       ARM_STRH_REG_REG_COND(p, rm, rd, rn, ARMCOND_AL)
+
+
 
 /* Swap */
 typedef struct {
@@ -713,6 +940,114 @@ typedef struct {
 
 
 
+
+#include "arm_dpimacros.h"
+
+#define ARM_NOP(p) ARM_MOV_REG_REG(p, ARMREG_R0, ARMREG_R0)
+
+
+#define ARM_SHL_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
+#define ARM_SHL_IMM(p, rd, rm, imm) \
+       ARM_SHL_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+#define ARM_SHLS_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, imm, cond)
+#define ARM_SHLS_IMM(p, rd, rm, imm) \
+       ARM_SHLS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+
+#define ARM_SHR_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
+#define ARM_SHR_IMM(p, rd, rm, imm) \
+       ARM_SHR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+#define ARM_SHRS_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, imm, cond)
+#define ARM_SHRS_IMM(p, rd, rm, imm) \
+       ARM_SHRS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+
+#define ARM_SAR_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
+#define ARM_SAR_IMM(p, rd, rm, imm) \
+       ARM_SAR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+#define ARM_SARS_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, imm, cond)
+#define ARM_SARS_IMM(p, rd, rm, imm) \
+       ARM_SARS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+
+#define ARM_ROR_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOV_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
+#define ARM_ROR_IMM(p, rd, rm, imm) \
+       ARM_ROR_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+#define ARM_RORS_IMM_COND(p, rd, rm, imm, cond) \
+       ARM_MOVS_REG_IMMSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, imm, cond)
+#define ARM_RORS_IMM(p, rd, rm, imm) \
+       ARM_RORS_IMM_COND(p, rd, rm, imm, ARMCOND_AL)
+
+#define ARM_SHL_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
+#define ARM_SHL_REG(p, rd, rm, rs) \
+       ARM_SHL_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SHLS_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSL, rs, cond)
+#define ARM_SHLS_REG(p, rd, rm, rs) \
+       ARM_SHLS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SHLS_REG_REG(p, rd, rm, rs) ARM_SHLS_REG(p, rd, rm, rs)
+
+#define ARM_SHR_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
+#define ARM_SHR_REG(p, rd, rm, rs) \
+       ARM_SHR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SHRS_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_LSR, rs, cond)
+#define ARM_SHRS_REG(p, rd, rm, rs) \
+       ARM_SHRS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SHRS_REG_REG(p, rd, rm, rs) ARM_SHRS_REG(p, rd, rm, rs)
+
+#define ARM_SAR_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
+#define ARM_SAR_REG(p, rd, rm, rs) \
+       ARM_SAR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SARS_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ASR, rs, cond)
+#define ARM_SARS_REG(p, rd, rm, rs) \
+       ARM_SARS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_SARS_REG_REG(p, rd, rm, rs) ARM_SARS_REG(p, rd, rm, rs)
+
+#define ARM_ROR_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOV_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
+#define ARM_ROR_REG(p, rd, rm, rs) \
+       ARM_ROR_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_RORS_REG_COND(p, rd, rm, rs, cond) \
+       ARM_MOVS_REG_REGSHIFT_COND(p, rd, rm, ARMSHIFT_ROR, rs, cond)
+#define ARM_RORS_REG(p, rd, rm, rs) \
+       ARM_RORS_REG_COND(p, rd, rm, rs, ARMCOND_AL)
+#define ARM_RORS_REG_REG(p, rd, rm, rs) ARM_RORS_REG(p, rd, rm, rs)
+
+#define ARM_DBRK(p) ARM_EMIT(p, 0xE6000010)
+#define ARM_IASM_DBRK() ARM_IASM_EMIT(0xE6000010)
+
+#define ARM_INC(p, reg) ARM_ADD_REG_IMM8(p, reg, reg, 1)
+#define ARM_DEC(p, reg) ARM_SUB_REG_IMM8(p, reg, reg, 1)
+
+
+/* ARM V5 */
+
+/* Count leading zeros, CLZ{cond} Rd, Rm */
+typedef struct {
+       arminstr_t rm   :  4;
+       arminstr_t tag2 :  8;
+       arminstr_t rd   :  4;
+       arminstr_t tag  :  12;
+       arminstr_t cond :  4;
+} ARMInstrCLZ;
+
+#define ARM_CLZ_ID 0x16F
+#define ARM_CLZ_ID2 0xF1
+#define ARM_CLZ_MASK ((0xFFF << 16) | (0xFF < 4))
+#define ARM_CLZ_TAG ((ARM_CLZ_ID << 16) | (ARM_CLZ_ID2 << 4))
+
+
+
+
 typedef union {
        ARMInstrBR    br;
        ARMInstrDPI   dpi;
@@ -727,22 +1062,16 @@ typedef union {
        ARMInstrSWI   swi;
        ARMInstrMSR   msr;
        ARMInstrMRS   mrs;
+       ARMInstrCLZ   clz;
 
        ARMInstrGeneric generic;
        arminstr_t      raw;
 } ARMInstr;
 
 
-#include "arm_dpimacros.h"
-
-#define ARM_NOP(p) ARM_MOV_REG_REG(p, ARMREG_R0, ARMREG_R0)
-
-
 #ifdef __cplusplus
 }
 #endif
 
 #endif /* ARM_H */
 
-
-

diff --git a/mono/arch/arm/arm-dis.c b/mono/arch/arm/arm-dis.c
index caec7e5f7679e8788d9de9d53a382dc2059ce436..0a478bc9f6bb1941876a44e5ff91050540e64b47 100644 (file)
--- a/mono/arch/arm/arm-dis.c
+++ b/mono/arch/arm/arm-dis.c
@@ -26,7 +26,7 @@ const static char* ops[] = {
 const static char* shift_types[] = {"lsl", "lsr", "asr", "ror"};
 
 const static char* mul_ops[] = {
-       "mul", "mla", "?", "?", "umul", "umlal", "smull", "smlal"
+       "mul", "mla", "?", "?", "umull", "umlal", "smull", "smlal"
 };
 
 const static char* reg_alias[] = {
@@ -58,6 +58,7 @@ void dump_mul(ARMDis* dis, ARMInstr i);
 void dump_swi(ARMDis* dis, ARMInstr i);
 void dump_swp(ARMDis* dis, ARMInstr i);
 void dump_wxfer(ARMDis* dis, ARMInstr i);
+void dump_clz(ARMDis* dis, ARMInstr i);
 
 
 /*
@@ -92,9 +93,9 @@ FILE* armdis_get_output(ARMDis* dis) {
 void dump_reg(ARMDis* dis, int reg) {
        reg &= 0xF;
        if (!use_reg_alias || (reg > 3 && reg < 11)) {
-                       fprintf(dis->dis_out, "r%d", reg);
+               fprintf(dis->dis_out, "r%d", reg);
        } else {
-                       fprintf(dis->dis_out, reg_alias[reg]);
+               fprintf(dis->dis_out, reg_alias[reg]);
        }
 }
 
@@ -136,28 +137,29 @@ void dump_reglist(ARMDis* dis, int reg_list) {
 
 
 void dump_br(ARMDis* dis, ARMInstr i) {
-       fprintf(dis->dis_out, "b%s%s\t%x",
+       fprintf(dis->dis_out, "b%s%s\t%x\t; %p -> %p",
            (i.br.link == 1) ? "l" : "",
-           cond[i.br.cond], i.br.offset);
+           cond[i.br.cond], i.br.offset, dis->pi, (int)dis->pi + 4*2 + ((int)(i.br.offset << 8) >> 6));
 }
 
 
 void dump_dpi(ARMDis* dis, ARMInstr i) {
        fprintf(dis->dis_out, "%s%s", ops[i.dpi.all.opcode], cond[i.dpi.all.cond]);
 
-       if ((i.dpi.all.opcode >= ARMOP_TST) && (i.dpi.all.opcode <= ARMOP_CMN) && (i.dpi.all.s != 0)) {
+       if ((i.dpi.all.opcode < ARMOP_TST || i.dpi.all.opcode > ARMOP_CMN) && (i.dpi.all.s != 0)) {
                fprintf(dis->dis_out, "s");
        }
 
        fprintf(dis->dis_out, "\t");
 
        if ((i.dpi.all.opcode < ARMOP_TST) || (i.dpi.all.opcode > ARMOP_CMN)) {
-               /* comparison operation */
+               /* for comparison operations Rd is ignored */
                dump_reg(dis, i.dpi.all.rd);
                fprintf(dis->dis_out, ", ");
        }
 
        if ((i.dpi.all.opcode != ARMOP_MOV) && (i.dpi.all.opcode != ARMOP_MVN)) {
+               /* for MOV/MVN Rn is ignored */
                dump_reg(dis, i.dpi.all.rn);
                fprintf(dis->dis_out, ", ");
        }
@@ -189,10 +191,11 @@ void dump_dpi(ARMDis* dis, ARMInstr i) {
 }
 
 void dump_wxfer(ARMDis* dis, ARMInstr i) {
-       fprintf(dis->dis_out, "%s%s%s\t",
+       fprintf(dis->dis_out, "%s%s%s%s\t",
                (i.wxfer.all.ls == 0) ? "str" : "ldr",
                cond[i.generic.cond],
-               (i.wxfer.all.b == 0) ? "" : "b");
+               (i.wxfer.all.b == 0) ? "" : "b",
+               (i.wxfer.all.ls != 0 && i.wxfer.all.wb != 0) ? "t" : "");
        dump_reg(dis, i.wxfer.all.rd);
        fprintf(dis->dis_out, ", [");
        dump_reg(dis, i.wxfer.all.rn);
@@ -277,7 +280,7 @@ void dump_mul(ARMDis* dis, ARMInstr i) {
                fprintf(dis->dis_out, ", ");
                dump_reg(dis, i.mul.rn);
                break;
-       case ARMOP_UMUL:
+       case ARMOP_UMULL:
        case ARMOP_UMLAL:
        case ARMOP_SMULL:
        case ARMOP_SMLAL:
@@ -372,6 +375,15 @@ void dump_swi(ARMDis* dis, ARMInstr i) {
 }
 
 
+void dump_clz(ARMDis* dis, ARMInstr i) {
+       fprintf(dis->dis_out, "clz%s\t");
+       dump_reg(dis, i.clz.rd);
+       fprintf(dis->dis_out, ", ");
+       dump_reg(dis, i.clz.rm);
+       fprintf(dis->dis_out, "\n");
+}
+
+
 
 void armdis_decode(ARMDis* dis, void* p, int size) {
        int i;
@@ -386,6 +398,7 @@ void armdis_decode(ARMDis* dis, void* p, int size) {
 
        for (i=0; i<size; ++i) {
                fprintf(dis->dis_out, "%p:\t%08x\t", pi, *pi);
+               dis->pi = pi;
                instr.raw = *pi++;
 
                if ((instr.raw & ARM_BR_MASK) == ARM_BR_TAG) {
@@ -394,6 +407,8 @@ void armdis_decode(ARMDis* dis, void* p, int size) {
                        dump_swp(dis, instr);
                } else if ((instr.raw & ARM_MUL_MASK) == ARM_MUL_TAG) {
                        dump_mul(dis, instr);
+               } else if ((instr.raw & ARM_CLZ_MASK) == ARM_CLZ_TAG) {
+                       dump_clz(dis, instr);
                } else if ((instr.raw & ARM_WXFER_MASK) == ARM_WXFER_TAG) {
                        dump_wxfer(dis, instr);
                } else if ((instr.raw & ARM_HXFER_MASK) == ARM_HXFER_TAG) {

diff --git a/mono/arch/arm/arm-dis.h b/mono/arch/arm/arm-dis.h
index b93db303ffa9c73b44ff3797d42e9141334c0ca5..8019499ce97e8a189a2a8c08d68cdb087793182b 100644 (file)
--- a/mono/arch/arm/arm-dis.h
+++ b/mono/arch/arm/arm-dis.h
@@ -14,6 +14,7 @@ extern "C" {
 
 typedef struct _ARMDis {
        FILE* dis_out;
+       void* pi;
 } ARMDis;
 
 

diff --git a/mono/arch/arm/cmp_macros.th b/mono/arch/arm/cmp_macros.th
index 8a357087a32f903c23d70c945ca71d71a98b77c2..cb2639dec1fb3433c4b243fab0aac0d8b6ac4f9b 100644 (file)
--- a/mono/arch/arm/cmp_macros.th
+++ b/mono/arch/arm/cmp_macros.th
@@ -1,11 +1,56 @@
-/* PSR = <Op> rd, (imm8 ROR 2*rot) */
-#define ARM_<Op>_REG_IMM_COND(p, rd, imm8, rot, cond) \
-       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_<Op>, rd, 0, imm8, rot, cond)
-#define ARM_<Op>_REG_IMM(p, rd, imm8, rot) \
-       ARM_<Op>_REG_IMM_COND(p, rd, imm8, rot, ARMCOND_AL)
-/* PSR = <Op> rd, imm8 */
-#define ARM_<Op>_REG_IMM8_COND(p, rd, imm8, cond) \
-       ARM_<Op>_REG_IMM_COND(p, rd, imm8, 0, cond)
-#define ARM_<Op>_REG_IMM8(p, rd, imm8) \
-       ARM_<Op>_REG_IMM8_COND(p, rd, imm8, ARMCOND_AL)
+/* PSR := <Op> Rn, (imm8 ROR 2*rot) */
+#define ARM_<Op>_REG_IMM_COND(p, rn, imm8, rot, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_<Op>, 0, rn, imm8, rot, cond)
+#define ARM_<Op>_REG_IMM(p, rn, imm8, rot) \
+       ARM_<Op>_REG_IMM_COND(p, rn, imm8, rot, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM_COND(rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_<Op>, 0, rn, imm8, rot, cond)
+#define _<Op>_REG_IMM(rn, imm8, rot) \
+       _<Op>_REG_IMM_COND(rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* PSR := <Op> Rn, imm8 */
+#define ARM_<Op>_REG_IMM8_COND(p, rn, imm8, cond) \
+       ARM_<Op>_REG_IMM_COND(p, rn, imm8, 0, cond)
+#define ARM_<Op>_REG_IMM8(p, rn, imm8) \
+       ARM_<Op>_REG_IMM8_COND(p, rn, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM8_COND(rn, imm8, cond) \
+       _<Op>_REG_IMM_COND(rn, imm8, 0, cond)
+#define _<Op>_REG_IMM8(rn, imm8) \
+       _<Op>_REG_IMM8_COND(rn, imm8, ARMCOND_AL)
+#endif
+
+
+/* PSR := <Op> Rn, Rm */
+#define ARM_<Op>_REG_REG_COND(p, rn, rm, cond) \
+       ARM_DPIOP_S_REG_REG_COND(p, ARMOP_<Op>, 0, rn, rm, cond)
+#define ARM_<Op>_REG_REG(p, rn, rm) \
+       ARM_<Op>_REG_REG_COND(p, rn, rm, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_REG_COND(rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_<Op>, 0, rn, rm, cond)
+#define _<Op>_REG_REG(rn, rm) \
+       _<Op>_REG_REG_COND(rn, rm, ARMCOND_AL)
+#endif
+
+
+/* PSR := <Op> Rn, (Rm <shift_type> imm8) */
+#define ARM_<Op>_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, cond) \
+       ARM_DPIOP_S_REG_IMMSHIFT_COND(p, ARMOP_<Op>, 0, rn, rm, shift_type, imm_shift, cond)
+#define ARM_<Op>_REG_IMMSHIFT(p, rn, rm, shift_type, imm_shift) \
+       ARM_<Op>_REG_IMMSHIFT_COND(p, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_<Op>, 0, rn, rm, shift_type, imm_shift, cond)
+#define _<Op>_REG_IMMSHIFT(rn, rm, shift_type, imm_shift) \
+       _<Op>_REG_IMMSHIFT_COND(rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
 

diff --git a/mono/arch/arm/dpi_macros.th b/mono/arch/arm/dpi_macros.th
index f8ec6086e92be77a37429c3a56c776163557a9d6..be43d1fe729ccd51970bdfdda8ef9cd4a5fcad09 100644 (file)
--- a/mono/arch/arm/dpi_macros.th
+++ b/mono/arch/arm/dpi_macros.th
@@ -1,6 +1,6 @@
 /* -- <Op> -- */
 
-/* rd = rn <Op> (imm8 ROR rot) ; rot is power of 2 */
+/* Rd := Rn <Op> (imm8 ROR rot) ; rot is power of 2 */
 #define ARM_<Op>_REG_IMM_COND(p, rd, rn, imm8, rot, cond) \
        ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_<Op>, rd, rn, imm8, rot, cond)
 #define ARM_<Op>_REG_IMM(p, rd, rn, imm8, rot) \
@@ -10,7 +10,19 @@
 #define ARM_<Op>S_REG_IMM(p, rd, rn, imm8, rot) \
        ARM_<Op>S_REG_IMM_COND(p, rd, rn, imm8, rot, ARMCOND_AL)
 
-/* rd = rn <Op> imm8 */
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_<Op>, rd, rn, imm8, rot, cond)
+#define _<Op>_REG_IMM(rd, rn, imm8, rot) \
+       _<Op>_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#define _<Op>S_REG_IMM_COND(rd, rn, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_<Op>, rd, rn, imm8, rot, cond)
+#define _<Op>S_REG_IMM(rd, rn, imm8, rot) \
+       _<Op>S_REG_IMM_COND(rd, rn, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn <Op> imm8 */
 #define ARM_<Op>_REG_IMM8_COND(p, rd, rn, imm8, cond) \
        ARM_<Op>_REG_IMM_COND(p, rd, rn, imm8, 0, cond)
 #define ARM_<Op>_REG_IMM8(p, rd, rn, imm8) \
@@ -20,8 +32,19 @@
 #define ARM_<Op>S_REG_IMM8(p, rd, rn, imm8) \
        ARM_<Op>S_REG_IMM8_COND(p, rd, rn, imm8, ARMCOND_AL)
 
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _<Op>_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _<Op>_REG_IMM8(rd, rn, imm8) \
+       _<Op>_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#define _<Op>S_REG_IMM8_COND(rd, rn, imm8, cond) \
+       _<Op>S_REG_IMM_COND(rd, rn, imm8, 0, cond)
+#define _<Op>S_REG_IMM8(rd, rn, imm8) \
+       _<Op>S_REG_IMM8_COND(rd, rn, imm8, ARMCOND_AL)
+#endif
+
 
-/* rd = rn <Op> rm */
+/* Rd := Rn <Op> Rm */
 #define ARM_<Op>_REG_REG_COND(p, rd, rn, rm, cond) \
        ARM_DPIOP_REG_REG_COND(p, ARMOP_<Op>, rd, rn, rm, cond)
 #define ARM_<Op>_REG_REG(p, rd, rn, rm) \
@@ -31,7 +54,19 @@
 #define ARM_<Op>S_REG_REG(p, rd, rn, rm) \
        ARM_<Op>S_REG_REG_COND(p, rd, rn, rm, ARMCOND_AL)
 
-/*  rd = rn <Op> (rm <shift_type> imm_shift) */
+#ifndef ARM_NOIASM
+#define _<Op>_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_<Op>, rd, rn, rm, cond)
+#define _<Op>_REG_REG(rd, rn, rm) \
+       _<Op>_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#define _<Op>S_REG_REG_COND(rd, rn, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_<Op>, rd, rn, rm, cond)
+#define _<Op>S_REG_REG(rd, rn, rm) \
+       _<Op>S_REG_REG_COND(rd, rn, rm, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn <Op> (Rm <shift_type> imm_shift) */
 #define ARM_<Op>_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, cond) \
        ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_<Op>, rd, rn, rm, shift_type, imm_shift, cond)
 #define ARM_<Op>_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
@@ -41,4 +76,37 @@
 #define ARM_<Op>S_REG_IMMSHIFT(p, rd, rn, rm, shift_type, imm_shift) \
        ARM_<Op>S_REG_IMMSHIFT_COND(p, rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
 
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_<Op>, rd, rn, rm, shift_type, imm_shift, cond)
+#define _<Op>_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _<Op>_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#define _<Op>S_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_<Op>, rd, rn, rm, shift_type, imm_shift, cond)
+#define _<Op>S_REG_IMMSHIFT(rd, rn, rm, shift_type, imm_shift) \
+       _<Op>S_REG_IMMSHIFT_COND(rd, rn, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+/* Rd := Rn <Op> (Rm <shift_type> Rs) */
+#define ARM_<Op>_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_<Op>, rd, rn, rm, shift_t, rs, cond)
+#define ARM_<Op>_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_<Op>_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define ARM_<Op>S_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_<Op>, rd, rn, rm, shift_t, rs, cond)
+#define ARM_<Op>S_REG_REGSHIFT(p, rd, rn, rm, shift_type, rs) \
+       ARM_<Op>S_REG_REGSHIFT_COND(p, rd, rn, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_<Op>, rd, rn, rm, shift_t, rs, cond)
+#define _<Op>_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _<Op>_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#define _<Op>S_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_<Op>, rd, rn, rm, shift_t, rs, cond)
+#define _<Op>S_REG_REGSHIFT(rd, rn, rm, shift_type, rs) \
+       _<Op>S_REG_REGSHIFT_COND(rd, rn, rm, shift_type, rs, ARMCOND_AL)
+#endif
+
 

diff --git a/mono/arch/arm/dpiops.sh b/mono/arch/arm/dpiops.sh
index 2eb43d9a75a0b5b050cbd217146eb34160a23cb5..ad394ae632b3120b56590a21846e46bedb7a1520 100755 (executable)
--- a/mono/arch/arm/dpiops.sh
+++ b/mono/arch/arm/dpiops.sh
@@ -28,5 +28,5 @@ echo -e "\n\n" >> $OUTFILE
 echo -e "\n/* DPIs, comparison */\n" >>  $OUTFILE
 gen "$CMP_OPCODES" cmp_macros
 
-echo -e "/* end generated */\n\n" >> $OUTFILE
+echo -e "\n/* end generated */\n" >> $OUTFILE
 

diff --git a/mono/arch/arm/mov_macros.th b/mono/arch/arm/mov_macros.th
index 151a29ba7179d5a21622a38241d11e7a09fcb5ba..6bac29003a9e9bf03fd6faca2b19210c12192694 100644 (file)
--- a/mono/arch/arm/mov_macros.th
+++ b/mono/arch/arm/mov_macros.th
@@ -1,18 +1,52 @@
-/* rd = imm8 ROR rot */
+/* Rd := imm8 ROR rot */
 #define ARM_<Op>_REG_IMM_COND(p, reg, imm8, rot, cond) \
        ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_<Op>, reg, 0, imm8, rot, cond)
 #define ARM_<Op>_REG_IMM(p, reg, imm8, rot) \
        ARM_<Op>_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
-#define ARM_<Op>_REG_IMM8(p, reg, imm8) \
-       ARM_<Op>_REG_IMM(p, reg, imm8, 0)
 /* S */
 #define ARM_<Op>S_REG_IMM_COND(p, reg, imm8, rot, cond) \
        ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_<Op>, reg, 0, imm8, rot, cond)
 #define ARM_<Op>S_REG_IMM(p, reg, imm8, rot) \
        ARM_<Op>S_REG_IMM_COND(p, reg, imm8, rot, ARMCOND_AL)
 
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_<Op>, reg, 0, imm8, rot, cond)
+#define _<Op>_REG_IMM(reg, imm8, rot) \
+       _<Op>_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+/* S */
+#define _<Op>S_REG_IMM_COND(reg, imm8, rot, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_<Op>, reg, 0, imm8, rot, cond)
+#define _<Op>S_REG_IMM(reg, imm8, rot) \
+       _<Op>S_REG_IMM_COND(reg, imm8, rot, ARMCOND_AL)
+#endif
+
+
+/* Rd := imm8 */
+#define ARM_<Op>_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_REG_IMM8ROT_COND(p, ARMOP_<Op>, reg, 0, imm8, 0, cond)
+#define ARM_<Op>_REG_IMM8(p, reg, imm8) \
+       ARM_<Op>_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+/* S */
+#define ARM_<Op>S_REG_IMM8_COND(p, reg, imm8, cond) \
+       ARM_DPIOP_S_REG_IMM8ROT_COND(p, ARMOP_<Op>, reg, 0, imm8, 0, cond)
+#define ARM_<Op>S_REG_IMM8(p, reg, imm8) \
+       ARM_<Op>S_REG_IMM8_COND(p, reg, imm8, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_REG_IMM8ROT_COND(ARMOP_<Op>, reg, 0, imm8, 0, cond)
+#define _<Op>_REG_IMM8(reg, imm8) \
+       _<Op>_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+/* S */
+#define _<Op>S_REG_IMM8_COND(reg, imm8, cond) \
+       ARM_IASM_DPIOP_S_REG_IMM8ROT_COND(ARMOP_<Op>, reg, 0, imm8, 0, cond)
+#define _<Op>S_REG_IMM8(reg, imm8) \
+       _<Op>S_REG_IMM8_COND(reg, imm8, ARMCOND_AL)
+#endif
+
 
-/* rd = rm */
+/* Rd := Rm */
 #define ARM_<Op>_REG_REG_COND(p, rd, rm, cond) \
        ARM_DPIOP_REG_REG_COND(p, ARMOP_<Op>, rd, 0, rm, cond)
 #define ARM_<Op>_REG_REG(p, rd, rm) \
@@ -23,9 +57,20 @@
 #define ARM_<Op>S_REG_REG(p, rd, rm) \
        ARM_<Op>S_REG_REG_COND(p, rd, rm, ARMCOND_AL)
 
+#ifndef ARM_NOIASM
+#define _<Op>_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_REG_REG_COND(ARMOP_<Op>, rd, 0, rm, cond)
+#define _<Op>_REG_REG(rd, rm) \
+       _<Op>_REG_REG_COND(rd, rm, ARMCOND_AL)
+/* S */
+#define _<Op>S_REG_REG_COND(rd, rm, cond) \
+       ARM_IASM_DPIOP_S_REG_REG_COND(ARMOP_<Op>, rd, 0, rm, cond)
+#define _<Op>S_REG_REG(rd, rm) \
+       _<Op>S_REG_REG_COND(rd, rm, ARMCOND_AL)
+#endif
 
 
-/*  rd = rm <shift_type> imm_shift */
+/* Rd := Rm <shift_type> imm_shift */
 #define ARM_<Op>_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, cond) \
        ARM_DPIOP_REG_IMMSHIFT_COND(p, ARMOP_<Op>, rd, 0, rm, shift_type, imm_shift, cond)
 #define ARM_<Op>_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
@@ -36,4 +81,41 @@
 #define ARM_<Op>S_REG_IMMSHIFT(p, rd, rm, shift_type, imm_shift) \
        ARM_<Op>S_REG_IMMSHIFT_COND(p, rd, rm, shift_type, imm_shift, ARMCOND_AL)
 
+#ifndef ARM_NOIASM
+#define _<Op>_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_REG_IMMSHIFT_COND(ARMOP_<Op>, rd, 0, rm, shift_type, imm_shift, cond)
+#define _<Op>_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _<Op>_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+/* S */
+#define _<Op>S_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, cond) \
+       ARM_IASM_DPIOP_S_REG_IMMSHIFT_COND(ARMOP_<Op>, rd, 0, rm, shift_type, imm_shift, cond)
+#define _<Op>S_REG_IMMSHIFT(rd, rm, shift_type, imm_shift) \
+       _<Op>S_REG_IMMSHIFT_COND(rd, rm, shift_type, imm_shift, ARMCOND_AL)
+#endif
+
+
+
+/* Rd := (Rm <shift_type> Rs) */
+#define ARM_<Op>_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_REG_REGSHIFT_COND(p, ARMOP_<Op>, rd, 0, rm, shift_type, rs, cond)
+#define ARM_<Op>_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_<Op>_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define ARM_<Op>S_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, cond) \
+       ARM_DPIOP_S_REG_REGSHIFT_COND(p, ARMOP_<Op>, rd, 0, rm, shift_type, rs, cond)
+#define ARM_<Op>S_REG_REGSHIFT(p, rd, rm, shift_type, rs) \
+       ARM_<Op>S_REG_REGSHIFT_COND(p, rd, rm, shift_type, rs, ARMCOND_AL)
+
+#ifndef ARM_NOIASM
+#define _<Op>_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_REG_REGSHIFT_COND(ARMOP_<Op>, rd, 0, rm, shift_type, rs, cond)
+#define _<Op>_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _<Op>_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+/* S */
+#define _<Op>S_REG_REGSHIFT_COND(rd, rm, shift_type, rs, cond) \
+       ARM_IASM_DPIOP_S_REG_REGSHIFT_COND(ARMOP_<Op>, rd, 0, rm, shift_type, rs, cond)
+#define _<Op>S_REG_REGSHIFT(rd, rm, shift_type, rs) \
+       _<Op>S_REG_REGSHIFT_COND(rd, rm, shift_type, rs, ARMCOND_AL)
+#endif
+