help
It sets PCI class to IDE compatible native mode, allowing
SeaBIOS, FILO etc... to boot from it.
+
+config DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1225
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1420
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_TI_PCI1520
+ select DRIVERS_TI
+ bool
+
+config DRIVERS_DEC_21143PD
+ bool
subdirs-y += generic/debug
subdirs-y += ati/ragexl
subdirs-y += sil/3114
+subdirs-y += ti/pcmcia-cardbus
+subdirs-y += dec/21143
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <device/device.h>
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <console/console.h>
+
+/**
+ * The following should be set in the mainboard-specific Kconfig file.
+ */
+#if (!defined(CONFIG_DEC21143_CACHE_LINE_SIZE) || \
+ !defined(CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS) || \
+ !defined(CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION))
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+/* CONFIG_DEC21143_CACHE_LINE_SIZE try 0x00000000 if unsure */
+/* CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS try 0x00000000 if unsure */
+/* CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION try 0x02800107 or 0x02800007 if unsure */
+
+/**
+ * This driver take the values from Kconfig and load them in the registers
+ */
+static void dec_21143pd_enable( device_t dev )
+{
+ printk( BIOS_DEBUG, "Init of DECchip 21143PD/TD Kconfig style\n");
+ // Command and Status Configuration Register (Offset 0x04)
+ pci_write_config32( dev, 0x04, CONFIG_DEC21143_COMMAND_AND_STATUS_CONFIGURATION );
+ printk( BIOS_DEBUG, "0x04 = %08x (07 01 80 02)\n", pci_read_config32(dev, 0x04) );
+ // Cache Line Size Register (Offset 0x0C)
+ pci_write_config8( dev, 0x0C, CONFIG_DEC21143_CACHE_LINE_SIZE );
+ printk( BIOS_DEBUG, "0x0c = %08x (00 80 00 00)\n", pci_read_config32(dev, 0x0C) );
+ // Expansion ROM Base Address Register (Offset 0x30)
+ pci_write_config32( dev, 0x30, CONFIG_DEC21143_EXPANSION_ROM_BASE_ADDRESS );
+ printk( BIOS_DEBUG, "0x30 = %08x (0x00000000)\n", pci_read_config32(dev, 0x30) );
+ return;
+}
+
+static struct device_operations dec_21143pd_ops = {
+ .read_resources = pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = dec_21143pd_enable,
+ .scan_bus = 0,
+};
+
+static const struct pci_driver dec_21143pd_driver __pci_driver = {
+ .ops = &dec_21143pd_ops,
+ .vendor = PCI_VENDOR_ID_DEC,
+ .device = PCI_DEVICE_ID_DEC_21142,
+};
--- /dev/null
+driver-$(CONFIG_DRIVERS_DEC_21143PD) += 21143pd.o
+
--- /dev/null
+driver-$(CONFIG_DRIVERS_TI) += ti-pcmcia-cardbus.o
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2010 Marc Bertens <mbertens@xs4all.nl>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <console/console.h>
+
+#if ( !defined( CONFIG_TI_PCMCIA_CARDBUS_CMDR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_CLSR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_CLTR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_BCR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_SCR ) || \
+ !defined( CONFIG_TI_PCMCIA_CARDBUS_MRR ) )
+#error "you must supply these values in your mainboard-specific Kconfig file"
+#endif
+
+static void ti_pci1x2y_init(struct device *dev)
+{
+ printk(BIOS_INFO, "Init of Texas Instruments PCI1x2x PCMCIA/CardBus controller\n");
+ // Command register (offset 04)
+ pci_write_config16( dev, 0x04, CONFIG_TI_PCMCIA_CARDBUS_CMDR );
+ // Cache Line Size Register (offset 0x0C)
+ pci_write_config8( dev, 0x0C, CONFIG_TI_PCMCIA_CARDBUS_CLSR );
+ // CardBus latency timer register (offset 1B)
+ pci_write_config8( dev, 0x1B, CONFIG_TI_PCMCIA_CARDBUS_CLTR );
+ // Bridge control register (offset 3E)
+ pci_write_config16( dev, 0x3E, CONFIG_TI_PCMCIA_CARDBUS_BCR );
+ /** Enable change sub-vendor id
+ * Clear the bit 5 to enable to write to the sub-vendor/device ids at 40 and 42 */
+ pci_write_config32( dev, 0x80, 0x10 );
+ pci_write_config32( dev, 0x40, PCI_VENDOR_ID_NOKIA );
+ // Now write the correct value for SCR
+ // System Control Register (offset 0x80)
+ pci_write_config32( dev, 0x80, CONFIG_TI_PCMCIA_CARDBUS_SCR );
+ // Multifunction routing register
+ pci_write_config32( dev, 0x8C, CONFIG_TI_PCMCIA_CARDBUS_MRR );
+ // Set Device Control Register (0x92) accordingly
+ pci_write_config8( dev, 0x92, pci_read_config8( dev, 0x92 ) | 0x02 );
+ return;
+}
+
+static struct device_operations ti_pci1x2y_ops = {
+ .read_resources = NULL, //pci_dev_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_dev_enable_resources,
+ .init = ti_pci1x2y_init,
+ .scan_bus = 0,
+};
+
+#ifdef CONFIG_DRIVERS_TI_PCI1225
+static const struct pci_driver ti_pci1225_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1225,
+};
+
+#endif
+#ifdef CONFIG_DRIVERS_TI_PCI1420
+static const struct pci_driver ti_pci1420_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+#endif
+#ifdef CONFIG_DRIVERS_TI_PCI1520
+static const struct pci_driver ti_pci1520_driver __pci_driver = {
+ .ops = &ti_pci1x2y_ops,
+ .vendor = PCI_VENDOR_ID_TI,
+ .device = PCI_DEVICE_ID_TI_1420,
+};
+#endif
+
+
#define PCI_DEVICE_ID_TI_4410 0xac41
#define PCI_DEVICE_ID_TI_4451 0xac42
#define PCI_DEVICE_ID_TI_1420 0xac51
+#define PCI_DEVICE_ID_TI_1520 0xAC55
#define PCI_VENDOR_ID_SONY 0x104d
#define PCI_DEVICE_ID_SONY_CXD3222 0x8039
#define PCI_DEVICE_ID_CCD_B00C 0xb00c
#define PCI_DEVICE_ID_CCD_B100 0xb100
+#define PCI_VENDOR_ID_NOKIA 0x13B8 // Nokia Telecommunications oy
+#define PCI_VENDOR_ID_NOKIA_WIRELESS 0x1603 // Nokia Wireless Communications
+#define PCI_VENDOR_ID_NOKIA_HOME 0x1622 // Nokia Home Communications
+
#define PCI_VENDOR_ID_3WARE 0x13C1
#define PCI_DEVICE_ID_3WARE_1000 0x1000
select NORTHBRIDGE_INTEL_I440BX
select SOUTHBRIDGE_INTEL_I82371EB
select SUPERIO_SMSC_SMSCSUPERIO
+ select DRIVERS_TI_PCI1225
+ select DRIVERS_DEC_21143PD
select ROMCC
+ select PIRQ_ROUTE
select HAVE_PIRQ_TABLE
select UDELAY_TSC
- select BOARD_ROMSIZE_KB_256
config MAINBOARD_DIR
string
config IRQ_SLOT_COUNT
int
- default 6
+ default 22
depends on BOARD_NOKIA_IP530
+## Configuration items for the ethernet adaptors
+config DEC21143_CACHE_LINE_SIZE
+ int
+ default 0x00000000
+ depends on BOARD_NOKIA_IP530
+
+config DEC21143_EXPANSION_ROM_BASE_ADDRESS
+ hex
+ default 0x00000000
+ depends on BOARD_NOKIA_IP530
+
+config DEC21143_COMMAND_AND_STATUS_CONFIGURATION
+ hex
+ default 0x02800107
+ depends on BOARD_NOKIA_IP530
+
+## Configuration for the PCMCIA-Cardbus controller.
+config TI_PCMCIA_CARDBUS_CMDR
+ hex
+ default 0x0107
+ depends on BOARD_NOKIA_IP530
+
+config TI_PCMCIA_CARDBUS_CLSR
+ hex
+ default 0x00
+ depends on BOARD_NOKIA_IP530
+
+config TI_PCMCIA_CARDBUS_CLTR
+ hex
+ default 0x40
+ depends on BOARD_NOKIA_IP530
+
+config TI_PCMCIA_CARDBUS_BCR
+ hex
+ default 0x07C0
+ depends on BOARD_NOKIA_IP530
+
+config TI_PCMCIA_CARDBUS_SCR
+ hex
+ default 0x08449060
+ depends on BOARD_NOKIA_IP530
+
+config TI_PCMCIA_CARDBUS_MRR
+ hex
+ default 0x00007522
+ depends on BOARD_NOKIA_IP530
chip southbridge/intel/i82371eb # Southbridge
device pci 7.0 on # ISA bridge
chip superio/smsc/smscsuperio # Super I/O (SMSC FDC37C878)
- device pnp 3f0.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 3f0.3 on # Parallel port
- io 0x60 = 0x378
- irq 0x70 = 7
- drq 0x74 = 4
- end
+ device pnp 3f0.0 off end # Floppy (No connector)
+ device pnp 3f0.3 off end # Parallel port (No connector)
device pnp 3f0.4 on # COM1
io 0x60 = 0x3f8
irq 0x70 = 4
io 0x60 = 0x2f8
irq 0x70 = 3
end
- device pnp 3f0.7 on # PS/2 keyboard / mouse
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1 # PS/2 keyboard interrupt
- irq 0x72 = 12 # PS/2 mouse interrupt
- end
- device pnp 3f0.9 on # Game port
- io 0x60 = 0x201
- end
- device pnp 3f0.a on # Power-management events (PME)
- io 0x60 = 0x600
- end
- device pnp 3f0.b on # MIDI port (MPU-401)
- io 0x60 = 0x330
- irq 0x70 = 5
- end
+ device pnp 3f0.7 on end # PS/2 keyboard / mouse
+ device pnp 3f0.6 on end # RTC
+ device pnp 3f0.8 on end # AUX I/O
+ device pnp 3f0.A off end # ACPI (No support yet)
end
end
device pci 7.1 on end # IDE
- device pci 7.2 on end # USB
- device pci 7.3 on end # ACPI
+ device pci 7.2 off end # USB (No connector)
+ device pci 7.3 off end # ACPI (No support yet)
register "ide0_enable" = "1"
register "ide1_enable" = "1"
register "ide_legacy_enable" = "1"
- # Enable UDMA/33 for higher speed if your IDE device(s) support it.
- register "ide0_drive0_udma33_enable" = "0"
- register "ide0_drive1_udma33_enable" = "0"
- register "ide1_drive0_udma33_enable" = "0"
- register "ide1_drive1_udma33_enable" = "0"
+ # Disable UDMA/33 for lower speed if your IDE device(s) don't support it.
+ register "ide0_drive0_udma33_enable" = "1"
+ register "ide0_drive1_udma33_enable" = "1"
+ register "ide1_drive0_udma33_enable" = "1"
+ register "ide1_drive1_udma33_enable" = "1"
end
- device pci 0d.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0e.0 on end # NIC (DEC DECchip 21142/43)
- device pci 0f.0 on end # CardBus bridge (TI PCI1225)
- device pci 0f.1 on end # CardBus bridge (TI PCI1225)
- end
- device pci_domain 1 on # PCI domain 1
- device pci 00.0 on end # PCI bridge (DEC DECchip 21150)
- end
- device pci_domain 2 on # PCI domain 2
- device pci 04.0 on end # NIC (DECchip 21142/43)
- device pci 04.0 on end # NIC (DECchip 21142/43)
end
end
-
0x122e, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x36, /* Checksum */
+ 0x44, /* Checksum */
{
- /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00, (0x07 << 3) | 0x0, {{0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x63, 0x0ea8}}, 0x0, 0x0},
- {0x00, (0x0c << 3) | 0x0, {{0x61, 0x06a8}, {0x62, 0x06a8}, {0x00, 0x06a8}, {0x00, 0x06a8}}, 0x0, 0x0},
- {0x00, (0x0d << 3) | 0x0, {{0x60, 0x0ea8}, {0x61, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x1, 0x0},
- {0x00, (0x09 << 3) | 0x0, {{0x62, 0x0ea8}, {0x63, 0x0ea8}, {0x60, 0x0ea8}, {0x61, 0x0ea8}}, 0x2, 0x0},
- {0x00, (0x0a << 3) | 0x0, {{0x63, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
- {0x01, (0x00 << 3) | 0x0, {{0x60, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}, {0x00, 0x0ea8}}, 0x0, 0x0},
+ /**
+ * Rebuild of the PIRQ table, to fix the non-working on-board NIC and PCMCIA controller.
+ */
+ // Southbridge 82371
+ { 0x00, (0x07 << 3) | 0x0, {{0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ // On-board PCI-to-PCI bridge
+ { 0x01, (0x00 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x0, 0x0 },
+ // ETH1 on front panel
+ { 0x00, (0x0d << 3) | 0x0, {{0x62, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH2 on front panel
+ { 0x00, (0x0e << 3) | 0x0, {{0x63, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH3 on front panel
+ { 0x02, (0x04 << 3) | 0x0, {{0x60, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // ETH4 on front panel
+ { 0x02, (0x05 << 3) | 0x0, {{0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // PCMCIA/Cardbus controller
+ { 0x00, (0x0f << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x00, 0x1E20}, {0x00, 0x1E20}}, 0x0, 0x0 },
+ // Bridge for slot 1 (top)
+ { 0x02, (0x07 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x64, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 1 (top)
+ { 0x03, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x1, 0x0 },
+ { 0x03, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x2, 0x0 },
+ { 0x03, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x3, 0x0 },
+ { 0x03, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x4, 0x0 },
+ // Bridge for slot 2 (middle)
+ { 0x02, (0x06 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 2 (middle)
+ { 0x04, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x5, 0x0 },
+ { 0x04, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0x6, 0x0 },
+ { 0x04, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0x7, 0x0 },
+ { 0x04, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0x8, 0x0 },
+ // Bridge for slot 3 (bottom)
+ { 0x00, (0x10 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x0, 0x0 },
+ // PCI compact slots 3 (bottom)
+ { 0x05, (0x04 << 3) | 0x0, {{0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}}, 0x9, 0x0 },
+ { 0x05, (0x05 << 3) | 0x0, {{0x62, 0x1E20}, {0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}}, 0xA, 0x0 },
+ { 0x05, (0x06 << 3) | 0x0, {{0x63, 0x1E20}, {0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}}, 0xB, 0x0 },
+ { 0x05, (0x07 << 3) | 0x0, {{0x60, 0x1E20}, {0x61, 0x1E20}, {0x62, 0x1E20}, {0x63, 0x1E20}}, 0xC, 0x0 },
}
};
{
return copy_pirq_routing_table(addr);
}
+
+/**
+ * TODO: This stub function is here until the point is solved in the
+ * main code of coreboot. see also arch/i386/boot/pirq_tables.c
+ */
+void pirq_assign_irqs(const unsigned char pIntAtoD[4])
+{
+ return;
+}
+
#include <device/device.h>
#include "chip.h"
+#include <device/pci_def.h>
+#include <device/pci.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <console/console.h>
+#define OUTB outb
+#define INB inb
+
+/*
+* Taken from flashrom project
+* Generic Super I/O helper functions
+*/
+static uint8_t sio_read(uint16_t port, uint8_t reg)
+{
+ OUTB( reg, port );
+ return ( INB( port + 1 ) );
+}
+
+static void sio_write(uint16_t port, uint8_t reg, uint8_t data)
+{
+ OUTB( reg, port );
+ OUTB( data, port + 1 );
+ return;
+}
+
+static void nokia_ip530_board_enable( device_t dev )
+{
+ print_debug( "Setting up IP530-Super I/O devices\n");
+ sio_write( 0x20, 0x03, 0x80 );
+ printk( BIOS_DEBUG, "--Register 0x03 = %X := 0x80\n", sio_read( 0x20, 0x03 ) );
+ sio_write( 0x20, 0x22, 0x30 );
+ printk( BIOS_DEBUG, "--Register 0x22 = %X := 0x30\n", sio_read( 0x20, 0x22 ) );
+ sio_write( 0x20, 0x24, 0x84 );
+ printk( BIOS_DEBUG, "--Register 0x24 = %X := 0x84\n", sio_read( 0x20, 0x24 ) );
+ return;
+}
struct chip_operations mainboard_ops = {
CHIP_NAME("Nokia IP530 Mainboard")
+ .enable_dev = nokia_ip530_board_enable,
};
projects / coreboot.git / commitdiff