Use existing, readable MTRR #defines instead of hardcoding numbers.

Replace $0x200 with $MTRRphysBase_MSR(0) etc. Also, move some #ifdef stuff
a little bit around (should not affect any functionality) to make the
Intel/AMD/VIA CAR implementations more similar and easier to compare.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Myles Watson <mylesgw@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5887 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index e4f1ba426d5c344ca35979f538410f989e1e2f62..a365ca8e3cdce6faef9de62097baf24f92751875 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -243,13 +243,13 @@ clear_fixed_var_mtrr_out:
 
 #if CacheSize > 0x8000
        /* enable caching for 32K-64K using fixed mtrr */
-       movl    $0x268, %ecx  /* fix4k_c0000*/
+       movl    $MTRRfix4K_C0000_MSR, %ecx
        simplemask CacheSize, 0x8000
        wrmsr
 #endif
 
        /* enable caching for 0-32K using fixed mtrr */
-       movl    $0x269, %ecx  /* fix4k_c8000*/
+       movl    $MTRRfix4K_C8000_MSR, %ecx
        simplemask CacheSize, 0
        wrmsr
 
@@ -260,22 +260,23 @@ clear_fixed_var_mtrr_out:
        wrmsr
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-       /* enable write base caching so we can do execute in place
-        * on the flash rom.
-        */
-       movl    $0x202, %ecx
-       xorl    %edx, %edx
 
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+
+       /* enable write base caching so we can do execute in place
+        * on the flash rom.
+        */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       xorl    %edx, %edx
        movl    $REAL_XIP_ROM_BASE, %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
-       movl    $0x203, %ecx
+       movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0xff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for K8 (CONFIG_CPU_ADDR_BITS = 40) */
        jmp_if_k8(wbcache_post_fam10_setup)
        movl    $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */

diff --git a/src/cpu/intel/car/cache_as_ram.inc b/src/cpu/intel/car/cache_as_ram.inc
index 105f920b135a5d2cc1b9ee5f1de578e94f119b98..0cf5a2e66961a6398bea044ff2669f5f8524b20c 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram.inc
+++ b/src/cpu/intel/car/cache_as_ram.inc
@@ -196,11 +196,13 @@ clear_fixed_var_mtrr_out:
        wrmsr
 
 #if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
+
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+
        /* enable write base caching so we can do execute in place
         * on the flash rom.
         */

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 4bbefef3cb1c09f36a7d201d352afb468751aa40..253c2143f09996e0d90b6ff748395d89a5e9091b 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -78,36 +78,33 @@ var_mtrr_msr:
        .long   0x000 /* NULL, end of table */
 
 clear_fixed_var_mtrr_out:
-       /* MTRRPhysBase */
-       movl    $0x200, %ecx
+       movl    $MTRRphysBase_MSR(0), %ecx
        xorl    %edx, %edx
        movl    $(CacheBase|MTRR_TYPE_WRBACK),%eax
        wrmsr
 
-       /* MTRRPhysMask */
-       movl    $0x201, %ecx
+       movl    $MTRRphysMask_MSR(0), %ecx
        /* This assumes we never access addresses above 2^36 in CAR. */
        movl    $0x0000000f,%edx
        movl    $(~(CacheSize-1)|0x800),%eax
        wrmsr
 
-       /* enable write base caching so we can do execute in place
-        * on the flash rom.
-        */
-       /* MTRRPhysBase */
-       movl    $0x202, %ecx
-       xorl    %edx, %edx
 #if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
 #define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
 #else
 #define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
 #endif
+
+       /* enable write base caching so we can do execute in place
+        * on the flash rom.
+        */
+       movl    $MTRRphysBase_MSR(1), %ecx
+       xorl    %edx, %edx
        movl    $REAL_XIP_ROM_BASE, %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
-       /* MTRRPhysMask */
-       movl    $0x203, %ecx
+       movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx
        movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
        wrmsr
@@ -195,8 +192,7 @@ testok:
 
 
        /* Set the default memory type and disable fixed and enable variable MTRRs */
-       movl    $0x2ff, %ecx
-       //movl    $MTRRdefType_MSR, %ecx
+       movl    $MTRRdefType_MSR, %ecx
        xorl    %edx, %edx
 
        /* Enable Variable and Disable Fixed MTRRs */
@@ -204,7 +200,7 @@ testok:
        wrmsr
 
        /* enable caching for first 1M using variable mtrr */
-       movl    $0x200, %ecx
+       movl    $MTRRphysBase_MSR(0), %ecx
        xorl    %edx, %edx
        movl     $(0 | 6), %eax
        //movl     $(0 | MTRR_TYPE_WRBACK), %eax
@@ -216,41 +212,41 @@ testok:
         * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
         */
 
-       movl    $0x201, %ecx
+       movl    $MTRRphysMask_MSR(0), %ecx
        movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
        movl    $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
        wrmsr
 
-       movl    $0x202, %ecx
+       movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
        movl     $(0x80000 | 6), %eax
        orl     $(0 | 6), %eax
        wrmsr
 
-       movl    $0x203, %ecx
+       movl    $MTRRphysMask_MSR(1), %ecx
        movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
        movl    $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
        wrmsr
 
-       movl    $0x204, %ecx
+       movl    $MTRRphysBase_MSR(2), %ecx
        xorl    %edx, %edx
        movl     $(0xc0000 | 6), %eax
        orl     $(0 | 6), %eax
        wrmsr
 
-       movl    $0x205, %ecx
+       movl    $MTRRphysMask_MSR(2), %ecx
        movl    $0x0000000f, %edx /* AMD 40 bit 0xff*/
        movl    $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
        wrmsr
 
        /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
-       movl    $0x206, %ecx
+       movl    $MTRRphysBase_MSR(3), %ecx
        xorl    %edx, %edx
        movl     $REAL_XIP_ROM_BASE,%eax
        orl     $(0 | 6), %eax
        wrmsr
 
-       movl    $0x207, %ecx
+       movl    $MTRRphysMask_MSR(3), %ecx
        xorl    %edx, %edx
        movl     $CONFIG_XIP_ROM_SIZE,%eax
        decl    %eax