msrtool: added support for Intel CPUs

[coreboot.git] / util / msrtool / intel_pentium3.c

diff --git a/util/msrtool/intel_pentium3.c b/util/msrtool/intel_pentium3.c
new file mode 100644 (file)
index 0000000..a2b4225
--- /dev/null
+++ b/util/msrtool/intel_pentium3.c
@@ -0,0 +1,182 @@
+/*
+ * This file is part of msrtool.
+ *
+ * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
+ */
+
+#include "msrtool.h"
+
+int intel_pentium3_probe(const struct targetdef *target) {
+       struct cpuid_t *id = cpuid();
+       return ((0x6 == id->family)&((0xa == id->model)|(0xb == id->model)));
+}
+
+const struct msrdef intel_pentium3_msrs[] = {
+       {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STAMP_COUNTER", "", {
+               { BITS_EOT }
+       }},
+       {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID", "", {
+               { BITS_EOT }
+       }},
+       {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
+               { BITS_EOT }
+       }},
+       {0x2a, MSRTYPE_RDWR, MSR2(0,0), "EBL_CR_POWERON", "", {
+               { BITS_EOT }
+       }},
+       {0x33, MSRTYPE_RDWR, MSR2(0,0), "TEST_CTL", "", {
+               { BITS_EOT }
+       }},
+       {0x3f, MSRTYPE_RDWR, MSR2(0,0), "THERM_DIODE_OFFSET", "", {
+               { BITS_EOT }
+       }},
+       {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
+               { BITS_EOT }
+       }},
+       {0xc1, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR0", "", {
+               { BITS_EOT }
+       }},
+       {0xc2, MSRTYPE_RDWR, MSR2(0,0), "PERFCTR1", "", {
+               { BITS_EOT }
+       }},
+       {0x11e, MSRTYPE_RDWR, MSR2(0,0), "BBL_CR_CTL3", "", {
+               { BITS_EOT }
+       }},
+       {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
+               { BITS_EOT }
+       }},
+       {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
+               { BITS_EOT }
+       }},
+       {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
+               { BITS_EOT }
+       }},
+       {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CONTROL", "", {
+               { BITS_EOT }
+       }},
+       {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
+               { BITS_EOT }
+       }},
+       {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLES", "", {
+               { BITS_EOT }
+       }},
+       {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
+               { BITS_EOT }
+       }},
+       {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE0", "", {
+               { BITS_EOT }
+       }},
+       {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK0", "", {
+               { BITS_EOT }
+       }},
+       {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE1", "", {
+               { BITS_EOT }
+       }},
+       {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK1", "", {
+               { BITS_EOT }
+       }},
+       {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE2", "", {
+               { BITS_EOT }
+       }},
+       {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK2", "", {
+               { BITS_EOT }
+       }},
+       {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE3", "", {
+               { BITS_EOT }
+       }},
+       {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK3", "", {
+               { BITS_EOT }
+       }},
+       {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE4", "", {
+               { BITS_EOT }
+       }},
+       {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK4", "", {
+               { BITS_EOT }
+       }},
+       {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE5", "", {
+               { BITS_EOT }
+       }},
+       {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK5", "", {
+               { BITS_EOT }
+       }},
+       {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE6", "", {
+               { BITS_EOT }
+       }},
+       {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK6", "", {
+               { BITS_EOT }
+       }},
+       {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSBASE7", "", {
+               { BITS_EOT }
+       }},
+       {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYSMASK7", "", {
+               { BITS_EOT }
+       }},
+       {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
+               { BITS_EOT }
+       }},
+       {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
+               { BITS_EOT }
+       }},
+       {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
+               { BITS_EOT }
+       }},
+       {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
+               { BITS_EOT }
+       }},
+       {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
+               { BITS_EOT }
+       }},
+       {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
+               { BITS_EOT }
+       }},
+       {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
+               { BITS_EOT }
+       }},
+       {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
+               { BITS_EOT }
+       }},
+       {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
+               { BITS_EOT }
+       }},
+       {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
+               { BITS_EOT }
+       }},
+       {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
+               { BITS_EOT }
+       }},
+       {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
+               { BITS_EOT }
+       }},
+       {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_CTL", "", {
+               { BITS_EOT }
+       }},
+       {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_STATUS", "", {
+               { BITS_EOT }
+       }},
+       {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_ADDR", "", {
+               { BITS_EOT }
+       }},
+       {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
+               { BITS_EOT }
+       }},
+       {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
+               { BITS_EOT }
+       }},
+       {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
+               { BITS_EOT }
+       }},
+       { MSR_EOT }
+};