AMD Agesa macro expansion fix

[coreboot.git] / src / vendorcode / amd / agesa / f14 / Proc / GNB / PCIe / Family / 0x14 / F14PcieWrapperServices.c

diff --git a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
index 330a02e3d0d1ada4549053b8a81e66889a7c4aff..3821ac711089a5b796544ef2e8664577124a6f61 100644 (file)
--- a/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
+++ b/src/vendorcode/amd/agesa/f14/Proc/GNB/PCIe/Family/0x14/F14PcieWrapperServices.c
@@ -263,12 +263,13 @@ PcieOnConfigureGppEnginesLaneAllocation (
   CoreLaneIndex = 0;
   PortIdIndex = 0;
   do {
+    if (PortIdIndex > 0) EnginesList++;
     EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
     EnginesList->Type.Port.PortId = GppPortIdConfigurationTable [ConfigurationId][PortIdIndex++];
     EnginesList->Type.Port.StartCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
     EnginesList->Type.Port.EndCoreLane = GppLaneConfigurationTable [ConfigurationId][CoreLaneIndex++];
 
-  } while (IS_LAST_DESCRIPTOR (EnginesList++));
+  } while (IS_LAST_DESCRIPTOR (EnginesList));
   return  AGESA_SUCCESS;
 }
 
@@ -305,12 +306,13 @@ PcieOnConfigureDdiEnginesLaneAllocation (
   }
   LaneIndex = 0;
   do {
+    if (LaneIndex > 0) EnginesList++;
     EnginesList->Flags &= ~DESCRIPTOR_ALLOCATED;
     EnginesList->EngineData.StartLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
                                         Wrapper->StartPhyLane;
     EnginesList->EngineData.EndLane = DdiLaneConfigurationTable [ConfigurationId][LaneIndex++] +
                                       Wrapper->StartPhyLane;
-  } while (IS_LAST_DESCRIPTOR (EnginesList++));
+  } while (IS_LAST_DESCRIPTOR (EnginesList));
   return  AGESA_SUCCESS;
 }