This does the following:

[coreboot.git] / src / southbridge / intel / i82801cx / i82801cx_reset.c

diff --git a/src/southbridge/intel/i82801cx/i82801cx_reset.c b/src/southbridge/intel/i82801cx/i82801cx_reset.c
new file mode 100644 (file)
index 0000000..20e8530
--- /dev/null
+++ b/src/southbridge/intel/i82801cx/i82801cx_reset.c
@@ -0,0 +1,8 @@
+#include <arch/io.h>
+
+void i82801cx_hard_reset(void)
+{
+        /* Try rebooting through port 0xcf9 */
+        // Hard reset without power cycle
+        outb((0 <<3)|(1<<2)|(1<<1), 0xcf9);
+}