Imported and merged Boehm GC 7.0

[cacao.git] / src / mm / boehm-gc / libatomic_ops-1.2 / src / atomic_ops / sysdeps / gcc / arm.h

diff --git a/src/mm/boehm-gc/libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/arm.h b/src/mm/boehm-gc/libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/arm.h
new file mode 100644 (file)
index 0000000..d1a3232
--- /dev/null
+++ b/src/mm/boehm-gc/libatomic_ops-1.2/src/atomic_ops/sysdeps/gcc/arm.h
@@ -0,0 +1,52 @@
+/* 
+ * Copyright (c) 1991-1994 by Xerox Corporation.  All rights reserved.
+ * Copyright (c) 1996-1999 by Silicon Graphics.  All rights reserved.
+ * Copyright (c) 1999-2003 by Hewlett-Packard Company. All rights reserved.
+ *
+ *
+ * THIS MATERIAL IS PROVIDED AS IS, WITH ABSOLUTELY NO WARRANTY EXPRESSED
+ * OR IMPLIED.  ANY USE IS AT YOUR OWN RISK.
+ *
+ * Permission is hereby granted to use or copy this program
+ * for any purpose,  provided the above notices are retained on all copies.
+ * Permission to modify the code and to distribute modified code is granted,
+ * provided the above notices are retained, and a notice that the code was
+ * modified is included with the above copyright notice.
+ *
+ */
+
+/* There exist multiprocessor SoC ARM processors, so this matters.     */
+/* This needs to be augmented for later ARM (e.g. V7) procesors.       */
+
+/* I found a slide set that, if I read it correctly, claims that       */
+/* Loads followed by either a Load or Store are ordered, but nothing   */
+/* else is.                                                            */
+/* It appears that SWP is the only simple memory barrier.              */
+#include "../all_atomic_load_store.h"
+
+#include "../read_ordered.h"
+
+#include "../test_and_set_t_is_ao_t.h" /* Probably suboptimal */
+
+
+AO_INLINE AO_TS_VAL_t
+AO_test_and_set_full(volatile AO_TS_t *addr) {
+  AO_TS_VAL_t oldval;
+  /* SWP on ARM is very similar to XCHG on x86.                */
+  /* The first operand is the result, the second the value     */
+  /* to be stored.  Both registers must be different from addr.        */
+  /* Make the address operand an early clobber output so it     */
+  /* doesn't overlap with the other operands.  The early clobber*/
+  /* on oldval is neccessary to prevent the compiler allocating */
+  /* them to the same register if they are both unused.        */
+  __asm__ __volatile__("swp %0, %2, [%3]"
+                        : "=&r"(oldval), "=&r"(addr)
+                        : "r"(1), "1"(addr)
+                        : "memory");
+  return oldval;
+}
+
+#define AO_HAVE_test_and_set_full
+
+
+