--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2006 Tyan
+ * Copyright (C) 2006 AMD
+ * Written by Yinghai Lu <yinghailu@gmail.com> for Tyan and AMD.
+ *
+ * Copyright (C) 2007 University of Mannheim
+ * Written by Philipp Degler <pdegler@rumms.uni-mannheim.de> for University of Mannheim
+ * Copyright (C) 2009 University of Heidelberg
+ * Written by Mondrian Nuessle <nuessle@uni-heidelberg.de> for University of Heidelberg
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#define RAMINIT_SYSINFO 1
+
+#define FAM10_SCAN_PCI_BUS 0
+#define FAM10_ALLOCATE_IO_RANGE 1
+
+#define QRANK_DIMM_SUPPORT 1
+
+#if CONFIG_LOGICAL_CPUS==1
+#define SET_NB_CFG_54 1
+#endif
+
+#define SET_FIDVID 1
+#define SET_FIDVID_CORE_RANGE 0
+
+#define DBGP_DEFAULT 7
+
+#include <stdint.h>
+#include <string.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include <console/console.h>
+#include "lib/ramtest.c"
+#include <cpu/amd/model_10xxx_rev.h>
+#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
+#include "northbridge/amd/amdfam10/raminit.h"
+#include "northbridge/amd/amdfam10/amdfam10.h"
+
+#include "cpu/amd/model_10xxx/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdfam10/reset_test.c"
+
+#include "superio/serverengines/pilot/pilot_early_serial.c"
+#include "superio/serverengines/pilot/pilot_early_init.c"
+#include "superio/nsc/pc87417/pc87417_early_serial.c"
+
+#include "cpu/x86/bist.h"
+
+#include "northbridge/amd/amdfam10/debug.c"
+
+#include "cpu/x86/mtrr/earlymtrr.c"
+
+//#include "northbridge/amd/amdfam10/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1)
+#define RTC_DEV PNP_DEV(0x4e, PC87417_RTC)
+
+#include "southbridge/broadcom/bcm5785/bcm5785_early_setup.c"
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ u8 val;
+ outb(0x3d, 0x0cd6);
+ outb(0x87, 0x0cd7);
+
+ outb(0x44, 0xcd6);
+ val = inb(0xcd7);
+ outb((val & ~3) | ctrl->spd_switch_addr, 0xcd7);
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdfam10/amdfam10.h"
+
+#include "northbridge/amd/amdfam10/raminit_sysinfo_in_ram.c"
+#include "northbridge/amd/amdfam10/amdfam10_pci.c"
+
+#include "cpu/amd/quadcore/quadcore.c"
+
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/microcode/microcode.c"
+#include "cpu/amd/model_10xxx/update_microcode.c"
+#include "cpu/amd/model_10xxx/init_cpus.c"
+
+#include "northbridge/amd/amdfam10/early_ht.c"
+
+#include "spd_addr.h"
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ struct sys_info *sysinfo = (struct sys_info *)(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+
+ u32 bsp_apicid = 0;
+ u32 val;
+ msr_t msr;
+
+ if (!cpu_init_detectedx && boot_cpu()) {
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ /* mov bsp to bus 0xff when > 8 nodes */
+ set_bsp_node_CHtExtNodeCfgEn();
+ enumerate_ht_chain();
+
+ /* Setup the rom access for 4M */
+ bcm5785_enable_rom();
+ bcm5785_enable_lpc();
+ //enable RTC
+ pc87417_enable_dev(RTC_DEV);
+ }
+
+ post_code(0x30);
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+ }
+
+ pilot_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
+
+ uart_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ console_init();
+ pilot_early_init(SERIAL_DEV); //config port is being taken from SERIAL_DEV
+
+ val = cpuid_eax(1);
+ printk(BIOS_DEBUG, "BSP Family_Model: %08x\n", val);
+ printk(BIOS_DEBUG, "*sysinfo range: [%p,%p]\n",sysinfo,sysinfo+1);
+ printk(BIOS_DEBUG, "bsp_apicid = %02x\n", bsp_apicid);
+ printk(BIOS_DEBUG, "cpu_init_detectedx = %08lx\n", cpu_init_detectedx);
+
+ /* Setup sysinfo defaults */
+ set_sysinfo_in_ram(0);
+
+ update_microcode(val);
+ post_code(0x33);
+
+ cpuSetAMDMSR();
+ post_code(0x34);
+
+ amd_ht_init(sysinfo);
+ post_code(0x35);
+
+ /* Setup nodes PCI space and start core 0 AP init. */
+ finalize_node_setup(sysinfo);
+
+ post_code(0x36);
+
+ /* wait for all the APs core0 started by finalize_node_setup. */
+ /* FIXME: A bunch of cores are going to start output to serial at once.
+ * It would be nice to fixup prink spinlocks for ROM XIP mode.
+ * I think it could be done by putting the spinlock flag in the cache
+ * of the BSP located right after sysinfo.
+ */
+
+ wait_all_core0_started();
+
+#if CONFIG_LOGICAL_CPUS==1
+ /* Core0 on each node is configured. Now setup any additional cores. */
+ printk(BIOS_DEBUG, "start_other_cores()\n");
+ start_other_cores();
+ post_code(0x37);
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+#if SET_FIDVID == 1
+ msr = rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "\nBegin FIDVID MSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+
+ /* FIXME: The sb fid change may survive the warm reset and only
+ * need to be done once.*/
+
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+ post_code(0x39);
+
+ if (!warm_reset_detect(0)) { // BSP is node 0
+ init_fidvid_bsp(bsp_apicid, sysinfo->nodes);
+ } else {
+ init_fidvid_stage2(bsp_apicid, 0); // BSP is node 0
+ }
+
+ post_code(0x3A);
+
+ /* show final fid and vid */
+ msr=rdmsr(0xc0010071);
+ printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x\n", msr.hi, msr.lo);
+#endif
+
+ init_timer();
+
+ /* Reset for HT, FIDVID, PLL and errata changes to take affect. */
+ if (!warm_reset_detect(0)) {
+ print_info("...WARM RESET...\n\n\n");
+ soft_reset();
+ die("After soft_reset_x - shouldn't see this message!!!\n");
+ }
+
+ /* It's the time to set ctrl in sysinfo now; */
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+ enable_smbus();
+
+ //do we need apci timer, tsc...., only debug need it for better output
+ /* all ap stopped? */
+// init_timer(); // Need to use TMICT to synconize FID/VID
+
+ printk(BIOS_DEBUG, "raminit_amdmct()\n");
+ raminit_amdmct(sysinfo);
+ post_code(0x41);
+
+ bcm5785_early_setup();
+
+ post_cache_as_ram();
+}
projects / coreboot.git / blobdiff