fix VIA C7 code.

[coreboot.git] / src / cpu / via / car / cache_as_ram.inc

diff --git a/src/cpu/via/car/cache_as_ram.inc b/src/cpu/via/car/cache_as_ram.inc
index 6389a3833f7a3a2f0f1aaabb56b2eae2b4d3b618..6bd2c0f393ccbdc241bd4fe7c354d82f673c57f2 100644 (file)
--- a/src/cpu/via/car/cache_as_ram.inc
+++ b/src/cpu/via/car/cache_as_ram.inc
@@ -100,7 +100,8 @@ clear_fixed_var_mtrr_out:
         */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-       movl    $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+       movl    $REAL_XIP_ROM_BASE, %eax
+       orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(1), %ecx
@@ -243,7 +244,8 @@ testok:
        /* Cache XIP_ROM_BASE-SIZE to speedup coreboot code. */
        movl    $MTRRphysBase_MSR(3), %ecx
        xorl    %edx, %edx
-       movl    $(REAL_XIP_ROM_BASE | MTRR_TYPE_WRBACK), %eax
+       movl    $REAL_XIP_ROM_BASE, %eax
+       orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
        movl    $MTRRphysMask_MSR(3), %ecx