Add RB_C3 to AMD_FAM10_ALL so that it gets its MSR right for mtrs, ht, etc.

[coreboot.git] / src / cpu / amd / model_10xxx / defaults.h

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 78c46d4eaf21ffce73e3411cdb8179ed7a23e25b..bddeb7c0f72c0f518ad6184cd0256b5a1a324d3f 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -136,27 +136,27 @@ static const struct {
         * program Link Global Extended Control Register[ForceFullT0]
         * (F0x16C[15:13]) to 000b */
 
-       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL, /* Fix FAM10_ALL when fixed in rev guide */
+       { 0, 0x170, AMD_DRBA23_RBC2, AMD_PTYPE_ALL, /* FIXME Should include BL_C2 but there is no constant */
          0x00000000, 0x00000100 },
-       { 0, 0x174, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x174,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x178, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x178,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x17C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x17C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x180, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x180,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x184, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x184,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x188, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x188,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x18C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x18C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
-       { 0, 0x170, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x170,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000000, 0x00000100 },
 
        /* Link Global Extended Control Register */
-       { 0, 0x16C, AMD_FAM10_ALL, AMD_PTYPE_ALL,
+       { 0, 0x16C,  AMD_DRBA23_RBC2, AMD_PTYPE_ALL,
          0x00000014, 0x0000003F },     /* [15:13] ForceFullT0 = 0b,
                                                                 * Set T0Time 14h per BKDG */