added rw-r port ram

[calu.git] / cpu / src / rw_r_ram.vhd

diff --git a/cpu/src/rw_r_ram.vhd b/cpu/src/rw_r_ram.vhd
new file mode 100644 (file)
index 0000000..0a4f06e
--- /dev/null
+++ b/cpu/src/rw_r_ram.vhd
@@ -0,0 +1,23 @@
+library IEEE;
+use IEEE.std_logic_1164.all;
+use IEEE.numeric_std.all;
+
+entity rw_r_ram is
+       generic (
+                               ADDR_WIDTH : integer range 1 to integer'high;
+                               DATA_WIDTH : integer range 1 to integer'high
+                       );
+       port(
+               --System inputs
+                       clk : in std_logic;
+               --Input
+                       rw_addr, rd_addr: in std_logic_vector(ADDR_WIDTH-1 downto 0);
+                       
+                       wr_en : in std_logic;
+                       data_in : in std_logic_vector(DATA_WIDTH-1 downto 0);
+                       
+               --Output
+                       rw_out, rd_out: out std_logic_vector(DATA_WIDTH-1 downto 0)
+               );
+               
+end entity rw_r_ram;